公开(公告)号：US20130320424A1

公开(公告)日：2013-12-05

申请号：US13601396

申请日：2012-08-31

申请人： Ki Hong LEE ,  Seung Ho PYI ,  Seok Min JEON

发明人： Ki Hong LEE ,  Seung Ho PYI ,  Seok Min JEON

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L27/11578 ,  H01L27/11519 ,  H01L27/11553 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/1158 ,  H01L27/11582 ,  H01L27/12 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7889 ,  H01L29/7926

摘要： A semiconductor device includes a first source layer; at least one of a second source layer, the second source layer formed substantially in the first source layer; a plurality of conductive layers stacked substantially over the first source layer; channel layers that pass through the plurality of conductive layers and couple to the second source layer; and at least one of a third source layer, the third source layer formed substantially in the second source layer, wherein the third source layer passes through the second source layer and is coupled to the first source layer.

摘要翻译： 半导体器件包括第一源极层; 第二源层中的至少一个，第二源极层基本上形成在第一源极层中; 基本上层叠在所述第一源极层上的多个导电层; 沟道层，其穿过所述多个导电层并耦合到所述第二源极层; 以及第三源层中的至少一个，所述第三源极层基本上形成在所述第二源极层中，其中所述第三源极层穿过所述第二源极层并且耦合到所述第一源极层。

公开(公告)号：US20130153978A1

公开(公告)日：2013-06-20

申请号：US13598528

申请日：2012-08-29

申请人： Ki Hong LEE ,  Seung Ho PYI ,  Seok Min JEON

发明人： Ki Hong LEE ,  Seung Ho PYI ,  Seok Min JEON

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L27/11582 ,  H01L29/66833 ,  H01L29/7926

摘要： A 3D non-volatile memory device includes a pipe gate, at least one first channel layer including a first pipe channel layer formed in the pipe gate and a pair of first source side channel layer and first drain side channel layer connected to the first pipe channel layer, and at least one second channel layer including a second pipe channel layer formed in the pipe gate and positioned over the first pipe channel layer and a pair of second source side channel layer and second drain side channel layer connected to the second pipe channel layer.