公开(公告)号：US20130145133A1

公开(公告)日：2013-06-06

申请号：US13690079

申请日：2012-11-30

申请人： Ki-Seok KWON ,  Jae-Un PARK ,  Suk-Jin KIM

发明人： Ki-Seok KWON ,  Jae-Un PARK ,  Suk-Jin KIM

IPC分类号： G06F9/30

CPC分类号： G06F9/3004 ,  G06F9/30043

摘要： A processor, apparatus and method to use a multiple store instruction based on physical addresses of registers are provided. The processor is configured to execute an instruction to store data of a plurality of registers in a memory, the instruction including a first area in which a physical address of each of the registers is written. An instruction generating apparatus is configured to generate an instruction to store data of a plurality of registers in a memory, the instruction including a first area in which a physical address of each of the registers is written. An instruction generating method includes detecting a code area that instructs to store data of a plurality of registers in a memory, from a program code. The instruction generating method further includes generating an instruction corresponding to the code area by mapping physical addresses of the registers to a first area of the instruction.

摘要翻译： 提供了一种基于寄存器的物理地址使用多存储指令的处理器，装置和方法。 处理器被配置为执行将多个寄存器的数据存储在存储器中的指令，该指令包括写入每个寄存器的物理地址的第一区域。 指令生成装置被配置为生成将多个寄存器的数据存储在存储器中的指令，该指令包括写入每个寄存器的物理地址的第一区域。 指令生成方法包括从程序代码检测指示将多个寄存器的数据存储在存储器中的代码区域。 指令生成方法还包括通过将寄存器的物理地址映射到指令的第一区域来生成与代码区域相对应的指令。

公开(公告)号：US20110225369A1

公开(公告)日：2011-09-15

申请号：US13036102

申请日：2011-02-28

申请人： Jae-Un PARK ,  Ki-Seok Kwon ,  Suk-Jin Kim

发明人： Jae-Un PARK ,  Ki-Seok Kwon ,  Suk-Jin Kim

IPC分类号： G06F12/08

CPC分类号： G06F12/0846 ,  G06F12/0857

摘要： A multiport data cache apparatus and a method of controlling the same are provided. The multiport data cache apparatus includes a plurality of cache banks configured to share a cache line, and a data cache controller configured to receive cache requests for the cache banks, each of which including a cache bank identifier, transfer the received cache requests to the respective cache banks according to the cache bank identifiers, and process the cache requests independently from one another.

摘要翻译： 提供了一种多端口数据缓存装置及其控制方法。 多端口数据高速缓存装置包括配置成共享高速缓存行的多个高速缓冲存储器组，以及数据高速缓存控制器，被配置为接收高速缓冲存储器的缓存请求，每个高速缓冲存储器包括高速缓存存储体标识符， 根据缓存存储体标识符缓存存储器，并且彼此独立地处理缓存请求。