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    Methods for forming integrated circuit capacitors including dual electrode depositions
    1.
    发明授权
    Methods for forming integrated circuit capacitors including dual electrode depositions 失效
    用于形成集成电路电容器的方法包括双电极沉积

    公开(公告)号：US5918135A

    公开(公告)日：1999-06-29

    申请号：US867070

    申请日：1997-06-02

    申请人： Ki-Young Lee ,  Kwang-Dong Yoo

    发明人： Ki-Young Lee ,  Kwang-Dong Yoo

    IPC分类号： H01L27/04 ,  H01L21/02 ,  H01L21/822 ,  H01L29/00 ,  H01L21/20

    CPC分类号： H01L28/60

    摘要： A method for forming an integrated circuit device includes the steps of forming a first capacitor electrode on a substrate and forming a first wiring electrode on the substrate. An insulating layer is formed on the first capacitor electrode and on the first wiring electrode opposite the substrate. A second capacitor electrode is formed on a portion of the insulating layer opposite the first capacitor electrode. A contact hole is formed in the insulating layer exposing a portion of the first wiring electrode. A second wiring electrode is then formed on the exposed portion of the wiring electrode, after forming the second capacitor electrode. Related structures are also discussed.

    摘要翻译： 一种形成集成电路器件的方法包括以下步骤：在衬底上形成第一电容器电极，并在衬底上形成第一布线电极。 绝缘层形成在第一电容器电极上和与基板相对的第一布线电极上。 第二电容器电极形成在与第一电容器电极相对的绝缘层的一部分上。 在绝缘层中形成暴露第一布线电极的一部分的接触孔。 在形成第二电容器电极之后，在布线电极的露出部分上形成第二布线电极。 还讨论了相关结构。

    Semiconductor devices with multiple isolation structure and methods for fabricating the same
    2.
    发明授权
    Semiconductor devices with multiple isolation structure and methods for fabricating the same 有权
    具有多重隔离结构的半导体器件及其制造方法

    公开(公告)号：US06815794B2

    公开(公告)日：2004-11-09

    申请号：US10373445

    申请日：2003-02-25

    申请人： Hwa-Sook Shin ,  Kwang-Dong Yoo

    发明人： Hwa-Sook Shin ,  Kwang-Dong Yoo

    IPC分类号： H01L2900

    CPC分类号： H01L21/8249 ,  H01L21/761 ,  H01L21/76237

    摘要： Semiconductor devices with a multiple isolation structure and methods for fabricating the same are provided. In one aspect, a semiconductor device comprises a heavily doped buried layer having a first conductivity type, which is formed in a predetermined region of a semiconductor substrate, and an epitaxial layer having the first conductivity type, which covers an entire surface of the semiconductor substrate. A device isolation structure is disposed such that the device isolation structure penetrates the epitaxial layer and a portion of the semiconductor substrate to define a device region. The device isolation structure includes an upper isolation structure penetrating an epitaxial layer as well as a lower isolation structure formed in the semiconductor substrate under the upper isolation structure.