公开(公告)号：US5321806A

公开(公告)日：1994-06-14

申请号：US748360

申请日：1991-08-21

申请人： Kim Meinerth ,  Colyn Case ,  Ali Moezzi ,  John Irwin ,  Agnes Masucci ,  Srinivasan Krishnaswami

发明人： Kim Meinerth ,  Colyn Case ,  Ali Moezzi ,  John Irwin ,  Agnes Masucci ,  Srinivasan Krishnaswami

IPC分类号： G06F9/38 ,  G06F12/08 ,  G09G5/06 ,  G09G5/08 ,  G09G5/36 ,  G09G5/39 ,  G06F15/20

CPC分类号： G09G5/363 ,  G06F9/3879 ,  G09G5/06 ,  G09G5/08 ,  G09G5/39 ,  G06F12/0831 ,  G09G2360/121 ,  G09G2360/127

摘要： A residue buffer, for temporary storage of portions of transmissions from a CPU to a graphics processor. Graphics commands are transmitted, in transmission units of uniform size, from a processor unit to an address generator, which processes the commands. The portion of the transmission unit not immediately usable by the graphics processor is stored in the residue buffer. The disclosure further describes a computer graphics system, having a graphics processor capable of reading from or writing to main memory, including virtual memory, without any action by the CPU; having a duplicate cache tag store accessible by the graphics system without generating traffic on the system bus; having a FIFO command buffer in main memory for temporary storage of graphics commands; having a "short circuit" feature for routing graphics commands to the command processor in the minimum number of steps; having a cursor control system capable of storing cursor pattern information in, and retrieving cursor pattern information from, main memory; having a cursor bus that is reconfigurable to carry information other than cursor information; and having a frame buffer module that contains no timing or cursor control circuitry.

摘要翻译： 一个残留缓冲器，用于临时存储从CPU到图形处理器的传输部分。 图形命令以统一大小的传输单元从处理器单元发送到处理命令的地址生成器。 不能由图形处理器立即使用的传输单元的部分被存储在剩余缓冲器中。 本公开进一步描述了一种计算机图形系统，其具有能够在没有CPU的任何动作的情况下能够从包括虚拟存储器的主存储器读取或写入的图形处理器; 具有由图形系统可访问的重复高速缓存标签存储器，而不在系统总线上产生流量; 在主存储器中具有用于临时存储图形命令的FIFO命令缓冲器; 具有用于以最小数量的步骤将图形命令路由到命令处理器的“短路”特征; 具有能够将光标图案信息存储在主存储器中并从主存储器检索光标图案信息的光标控制系统; 具有可重配置以携带除光标信息之外的信息的光标总线; 并具有不包含定时或光标控制电路的帧缓冲器模块。