公开(公告)号：US5828895A

公开(公告)日：1998-10-27

申请号：US531882

申请日：1995-09-20

Applicant: Kin Shing Chan ,  Ravindra Kumar Nair

Inventor： Kin Shing Chan ,  Ravindra Kumar Nair

IPC: G06F9/30 ,  G06F9/32 ,  G06F9/38

CPC classification number: G06F9/382 ,  G06F9/30094 ,  G06F9/30163 ,  G06F9/30167 ,  G06F9/3836 ,  G06F9/3838 ,  G06F9/384 ,  G06F9/3857 ,  G06F9/3885

Abstract: In response to reloading an instruction from main memory for storing in an instruction cache in a superscalar data processing system, a particular instruction category in which the instruction belongs is selected from multiple instruction categories. Types of data processing system resources required for instruction execution and a quantity of each type of resource required are determined. Thereafter, a plurality of decode bits are calculated, wherein the decode bits represent a particular instruction category in which the instruction belongs and the type and quantity of each data processing system resource required for execution of the instruction. Thereafter, the instruction and the predecode bits are stored in instruction cache. The predecode bits enable the dispatch unit to efficiently, and without fully decoding the instruction at dispatch time, select an execution unit for executing the instruction and determine if the data processing system resources required for execution of the instruction are available before the dispatch unit dispatches the instruction.

Abstract translation: 响应于从主存储器重新加载用于存储在超标量数据处理系统中的指令高速缓存中的指令，从多个指令类别中选择指令所属的特定指令类别。 确定指令执行所需的数据处理系统资源的类型和所需的每种类型的资源的数量。 此后，计算多个解码位，其中解码位表示指令所属的特定指令类别以及执行指令所需的每个数据处理系统资源的类型和数量。 此后，指令和预解码位存储在指令高速缓存中。 预分解位使得调度单元能够有效地并且在调度时没有完全解码指令的情况下，选择用于执行指令的执行单元，并且在调度单元调度之前确定执行指令所需的数据处理系统资源是否可用 指令。

公开(公告)号：US06195746B1

公开(公告)日：2001-02-27

申请号：US08791895

申请日：1997-01-31

Applicant: Ravindra Kumar Nair

Inventor： Ravindra Kumar Nair

IPC: G06F1500

CPC classification number: G06F9/3885 ,  G06F9/30094 ,  G06F9/30105 ,  G06F9/30112 ,  G06F9/3016 ,  G06F9/30192 ,  G06F9/3891

Abstract: Dynamically typed registers in a processor are provided by associating a type specifier with a register specifier for each register in the processor, storing the register specifiers and associated type specifiers in a register type table. The type specifier associated with an operand register of an instruction is employed to dispatch the instruction to an appropriate execution unit within the processor. The results of the instruction are stored in a register having an associated type specifier matching the execution unit type. Register specifiers are dynamically allocated to particular execution units within the processor by altering the type specifier associated with the register specifiers. Register values may be either discarded or converted when the register specifier type is altered. A general instruction allows conversion of the value from one type to another without storing the converted value in memory.

Abstract translation: 通过将类型说明符与处理器中的每个寄存器的寄存器说明符相关联来提供处理器中的动态类型寄存器，将寄存器说明符和相关联的类型说明符存储在寄存器类型表中。 与指令的操作数寄存器相关联的类型说明符用于将指令分派到处理器内的适当的执行单元。 指令的结果存储在具有与执行单元类型相匹配的相关联的类型说明符的寄存器中。 寄存器说明符通过改变与寄存器说明符相关联的类型说明符来动态分配给处理器内的特定执行单元。 当寄存器说明符类型被更改时，寄存器值可以被丢弃或转换。 通用指令允许将值从一种类型转换为另一种类型，而不将转换的值存储在内存中。

公开(公告)号：US5794027A

公开(公告)日：1998-08-11

申请号：US803649

申请日：1997-02-21

Applicant: Gregory Frederick Grohoski ,  Ravindra Kumar Nair

Inventor： Gregory Frederick Grohoski ,  Ravindra Kumar Nair

IPC: G06F9/38 ,  G06F12/08

CPC classification number: G06F9/3804

Abstract: A small buffer called a branch-anticipate buffer (BAB) is used to store groups of instructions which are likely to be required from the instruction cache (I-cache) when an instruction prefetch miss occurs. When a prefetch miss occurs, the BAB is checked to see if instructions corresponding to the target address are available. If they are available, these instructions are copied into an appropriate buffer. If the instructions corresponding to the target address are unavailable, these instructions are fetched from the I-cache and placed into a buffer and, selectively, into the BAB. The BAB only maintains branch target addresses that have not been previously scanned and that cannot be prefetched in time. This allows for smaller buffer sizes, and resulting quicker access time, when checking the BAB for instructions to be executed by a processor.

Abstract translation: 称为分支预期缓冲器（BAB）的小型缓冲器用于存储当发生指令预取缺失时可能从指令高速缓存（I-cache）需要的指令组。 当发生预取未命中时，检查BAB以查看与目标地址相对应的指令是否可用。 如果可用，这些指令将被复制到适当的缓冲区。 如果与目标地址相对应的指令不可用，则从I缓存中取出这些指令，并将其放入缓冲区，并有选择地放入BAB。 BAB仅维护尚未先前扫描并且不能及时预取的分支目标地址。 当检查BAB以获得由处理器执行的指令时，这允许较小的缓冲区大小，并导致更快的访问时间。