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公开(公告)号：US08213489B2
公开(公告)日：2012-07-03
申请号：US11206314
申请日：2005-08-17
IPC分类号： H04B1/38
CPC分类号： H04M3/005 , H04L5/1423 , H04L25/0266
摘要： The invention provides a communication protocol and serial interface having an approximately fixed interface clock and capable of accommodating a variety of communication rates. The interface employs a variable-length frame that may be expanded or reduced to obtain a desired communication rate, even though the interface clock rate is held approximately constant. The invention further provides a method for designing an agile barrier interface. In particular, the barrier clock rate is preferably selected to be an approximate common multiple of the various communication rates that the barrier interface must handle. The frame length corresponding to each communication rate may then be obtained by dividing the barrier clock rate by the ΣΔ rate. Finally, the invention provides an agile barrier capable of communicating data across a serial interface at a variety of data rates and at an approximately fixed interface clock rate.
摘要翻译： 本发明提供一种通信协议和串行接口，其具有近似固定的接口时钟并且能够适应各种通信速率。 接口采用可扩展或缩小的可变长度帧，以获得期望的通信速率，即使接口时钟速率保持近似恒定。 本发明还提供了一种用于设计敏捷屏障界面的方法。 特别地，屏障时钟速率优选地被选择为屏障接口必须处理的各种通信速率的近似公倍数。 然后可以通过将屏障时钟速率除以＆Sgr＆amp; Dgr来获得对应于每个通信速率的帧长度; 率。 最后，本发明提供了能够以各种数据速率和大致固定的接口时钟速率通过串行接口传送数据的敏捷障碍。
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公开(公告)号：US20090108883A1
公开(公告)日：2009-04-30
申请号：US11982264
申请日：2007-10-31
IPC分类号： H03B21/00
CPC分类号： H03B28/00
摘要： In accordance with described exemplary embodiments, correction is inserted into the feedback loop of a second order resonator used at the time of frequency transition. The correction is based upon parameters generated from a desired output signal frequency and a desired sampling frequency. The correction is generated to maintain i) constant amplitude, ii) continuous phase, and iii) the same sampling frequency during the frequency transition.
摘要翻译： 根据所描述的示例性实施例，校正被插入到在频率转换时使用的二阶谐振器的反馈回路中。 校正基于从期望的输出信号频率和期望的采样频率产生的参数。 产生校正以维持i）恒定幅度，ii）连续相位，以及iii）频率转换期间相同的采样频率。
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公开(公告)号：US07471123B2
公开(公告)日：2008-12-30
申请号：US11109701
申请日：2005-04-20
申请人： William Eric Holland , Wenzhe Luo , Zhigang Ma , Dale H. Nelson , Harold Thomas Simmonds , Lizhong Sun , Xiangqun Sun
发明人： William Eric Holland , Wenzhe Luo , Zhigang Ma , Dale H. Nelson , Harold Thomas Simmonds , Lizhong Sun , Xiangqun Sun
IPC分类号： H03K21/00
CPC分类号： G06F7/68 , H03L7/1976
摘要： A baseband clock synthesizer having particular use in a BLUETOOTH piconet device, having the capability of generating either 12 MHz or 13 MHz clock signals generated from any reference clock signal, e.g., 12.00, 12.80, 13.00, 15.36, 16.80, 19.20, 19.44, 19.68, 19.80, and 26.00 MHz. A fractional-N frequency divider is implemented with a PLL including a variable divider allowing the use of virtually any reference frequency input to generate a locked 156 MHz clock signal used as a basis for a 12 MHz or 13 MHz baseband clock signal. A residue feedback sigma-delta modulator provides a varying integer sequence to an integer divider in a feedback path of the PLL, effectively allowing division by non-integer numbers in the PLL. Thus, the PLL can be referenced to virtually any reference clock and still provide a fixed output clock signal (e.g., 12 or 13 MHz).
摘要翻译： 具有在BLUETOOTH微微网器件中特别使用的基带时钟合成器，具有产生从任何参考时钟信号（例如12.00,12.80,13.00,15.36,16.80,19.20,15.46,19.80,19.20,19.44,19.68）产生的12MHz或13MHz时钟信号的能力。 ，19.80和26.00MHz。 分数N分频器由PLL包括可变分频器实现，允许使用实际上任何参考频率输入来产生用作12MHz或13MHz基带时钟信号的基础的锁定的156MHz时钟信号。 残留反馈Σ-Δ调制器在PLL的反馈路径中向整数分频器提供变化的整数序列，有效地允许在PLL中除以非整数。 因此，PLL可以参考实际上任何参考时钟，并且仍然提供固定的输出时钟信号（例如，12或13MHz）。
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公开(公告)号：US08082285B2
公开(公告)日：2011-12-20
申请号：US11982264
申请日：2007-10-31
IPC分类号： G06F1/02
CPC分类号： H03B28/00
摘要： In accordance with described exemplary embodiments, correction is inserted into the feedback loop of a second order resonator used at the time of frequency transition. The correction is based upon parameters generated from a desired output signal frequency and a desired sampling frequency. The correction is generated to maintain i) constant amplitude, ii) continuous phase, and iii) the same sampling frequency during the frequency transition.
摘要翻译： 根据所描述的示例性实施例，校正被插入到在频率转换时使用的二阶谐振器的反馈回路中。 校正基于从期望的输出信号频率和期望的采样频率产生的参数。 产生校正以维持i）恒定幅度，ii）连续相位，以及iii）在频率转换期间相同的采样频率。
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公开(公告)号：US06946884B2
公开(公告)日：2005-09-20
申请号：US10131210
申请日：2002-04-25
申请人： William Eric Holland , Wenzhe Luo , Zhigang Ma , Dale H. Nelson , Harold Thomas Simmonds , Lizhong Sun , Xiangqun Sun
发明人： William Eric Holland , Wenzhe Luo , Zhigang Ma , Dale H. Nelson , Harold Thomas Simmonds , Lizhong Sun , Xiangqun Sun
CPC分类号： G06F7/68 , H03L7/1976
摘要： A baseband clock synthesizer having particular use in a BLUETOOTH piconet device, having the capability of generating either 12 MHz or 13 MHz clock signals generated from any reference clock signal, e.g., 12.00, 12.80, 13.00, 15.36, 16.80, 19.20, 19.44, 19.68, 19.80, and 26.00 MHz. A fractional-N frequency divider is implemented with a PLL including a variable divider allowing the use of virtually any reference frequency input to generate a locked 156 MHz clock signal used as a basis for a 12 MHz or 13 MHz baseband clock signal. A residue feedback sigma-delta modulator provides a varying integer sequence to an integer divider in a feedback path of the PLL, effectively allowing division by non-integer numbers in the PLL. Thus, the PLL can be referenced to virtually any reference clock and still provide a fixed output clock signal (e.g., 12 or 13 MHz).
摘要翻译： 具有在BLUETOOTH微微网器件中特别使用的基带时钟合成器，具有产生从任何参考时钟信号（例如12.00,12.80,13.00,15.36,16.80,19.20,15.46,19.80,19.20,19.44,19.68）产生的12MHz或13MHz时钟信号的能力。 ，19.80和26.00MHz。 分数N分频器由PLL包括可变分频器实现，允许使用实际上任何参考频率输入来产生用作12MHz或13MHz基带时钟信号的基础的锁定的156MHz时钟信号。 残留反馈Σ-Δ调制器在PLL的反馈路径中向整数分频器提供变化的整数序列，有效地允许在PLL中除以非整数。 因此，PLL可以参考实际上任何参考时钟，并且仍然提供固定的输出时钟信号（例如，12或13MHz）。
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