公开(公告)号：US20210335401A1

公开(公告)日：2021-10-28

申请号：US17121231

申请日：2020-12-14

Applicant: Kioxia Corporation

Inventor： Yutaka SHIMIZU ,  Satoshi INOUE ,  Isao FUJISAWA ,  Yumi TAKADA

IPC: G11C7/10

Abstract: According to one embodiment, there is provided a semiconductor integrated circuit including an input circuit. The input circuit includes a first amplifier and a second amplifier. The second amplifier is electrically connected to the first amplifier. The second amplifier includes a first transistor, a second transistor, a third transistor, a fourth transistor, and a time constant providing circuit. The first transistor has a gate electrically connected to a first node of the first amplifier. The second transistor has a gate electrically connected to a second node of the first amplifier. The third transistor is disposed adjacent to a drain of the first transistor. The fourth transistor is disposed adjacent to a drain of the second transistor. The time constant providing circuit is electrically connected between a gate of the third transistor and a drain of the third transistor, a gate of the fourth transistor.

公开(公告)号：US20240195372A1

公开(公告)日：2024-06-13

申请号：US18489140

申请日：2023-10-18

Applicant: Kioxia Corporation

Inventor： Yutaka SHIMIZU ,  Yasuhiro HIRASHIMA ,  Isao FUJISAWA ,  Michael BURGHART ,  Yuanlun ZHANG

IPC: H03F3/45 ,  H10B41/30 ,  H10B43/30

CPC classification number: H03F3/45659 ,  H10B41/30 ,  H10B43/30 ,  H03F2203/45091

Abstract: An amplifier of an input circuit includes: a first PMOS transistor having a gate connected to a first node, a source connected to a second node, and a drain connected to a third node; a second PMOS transistor having a gate connected to a fourth node that inputs a reference signal, a source connected to the second node, and a drain connected to a fifth node; a current source connected between a power supply voltage and the second node; a load circuit connected between the third node and a ground voltage; a first NMOS transistor having a gate connected to the first node, a drain connected to the power supply voltage, and a source connected to the fifth node; and a second NMOS transistor having a gate connected to the fourth node, a drain connected to the power supply voltage, and a source connected to the third node.