公开(公告)号：US20210335401A1

公开(公告)日：2021-10-28

申请号：US17121231

申请日：2020-12-14

Applicant: Kioxia Corporation

Inventor： Yutaka SHIMIZU ,  Satoshi INOUE ,  Isao FUJISAWA ,  Yumi TAKADA

IPC: G11C7/10

Abstract: According to one embodiment, there is provided a semiconductor integrated circuit including an input circuit. The input circuit includes a first amplifier and a second amplifier. The second amplifier is electrically connected to the first amplifier. The second amplifier includes a first transistor, a second transistor, a third transistor, a fourth transistor, and a time constant providing circuit. The first transistor has a gate electrically connected to a first node of the first amplifier. The second transistor has a gate electrically connected to a second node of the first amplifier. The third transistor is disposed adjacent to a drain of the first transistor. The fourth transistor is disposed adjacent to a drain of the second transistor. The time constant providing circuit is electrically connected between a gate of the third transistor and a drain of the third transistor, a gate of the fourth transistor.

公开(公告)号：US20210295930A1

公开(公告)日：2021-09-23

申请号：US17118703

申请日：2020-12-11

Applicant: Kioxia Corporation

Inventor： Fumiya WATANABE ,  Masaru KOYANAGI ,  Yutaka SHIMIZU ,  Yasuhiro HIRASHIMA ,  Kei SHIRAISHI ,  Mikihiko ITO

IPC: G11C16/32 ,  G11C7/10 ,  G11C16/10

Abstract: According to one embodiment, in a semiconductor integrated circuit, an input circuit has an input and an output stage electrically connected to the input stage via a first node and a second node. The input stage includes a first transistor, a second transistor, a third transistor, a fourth transistor, a first time constant adjusting circuit and a second time constant adjusting circuit. The first transistor has a gate that receives an input signal. The second transistor has a gate that receives a reference signal. The third transistor is disposed adjacent to a drain of the first transistor. The fourth transistor is disposed adjacent to a drain of the second transistor. The first time constant adjusting circuit is electrically connected between a gate of the third transistor and the first node. The second time constant adjusting circuit is electrically connected between a gate of the fourth transistor and the second node.

公开(公告)号：US20210090633A1

公开(公告)日：2021-03-25

申请号：US16803260

申请日：2020-02-27

Applicant: KIOXIA CORPORATION

Inventor： Rui ITO ,  Makoto MORIMOTO ,  Yutaka SHIMIZU ,  Ryuichi FUJIMOTO

IPC: G11C11/4074 ,  G11C11/408 ,  G11C11/4076 ,  G11C16/34 ,  G11C7/10

Abstract: According to one embodiment, a semiconductor memory device includes a plurality of memory cells connected to a word line, a circuit configured to apply a voltage to the word line, a detection circuit configured to detect a first time difference from when a first signal of which a voltage is increased with a first slope is applied to the word line to when a current flows through the memory cells in response to applying the first signal, and a second time difference from when a second signal of which a voltage is increased with a second slope is applied to the word line to when a current flows through the memory cells in response to applying the second signal, the second slope being different from the first slope, and a determination circuit configured to determine a threshold voltage of the memory cells based on a difference between the first time difference and the second time difference.

公开(公告)号：US20240324220A1

公开(公告)日：2024-09-26

申请号：US18604848

申请日：2024-03-14

Applicant: KIOXIA CORPORATION

Inventor： Yoshikazu HOSOMURA ,  Go OIKE ,  Yutaka SHIMIZU ,  Masaki NAKAMURA ,  Hironobu HAMANAKA ,  Hideo WADA

IPC: H10B43/27 ,  H01L23/00 ,  H01L25/065 ,  H01L25/18 ,  H10B80/00

CPC classification number: H10B43/27 ,  H01L24/08 ,  H01L25/0657 ,  H01L25/18 ,  H10B80/00 ,  H01L2224/08145 ,  H01L2924/1431 ,  H01L2924/14511

Abstract: A semiconductor memory device comprises: a substrate; a first wiring layer; a second wiring layer provided between the substrate and the first wiring layer; and a memory cell array layer provided between the substrate and the second wiring layer. The memory cell array layer comprises a contact extending in a first direction intersecting with a surface of the substrate. The first wiring layer has a second conductive layer that includes a connecting portion, a pad electrode portion, and a peripheral edge portion. The connecting portion is connected to one end in the first direction of the contact. The second wiring layer has: a first opening which is provided in a region including the connecting portion and the pad electrode portion of the second conductive layer; and a ring-shaped first slit which surrounds the peripheral edge portion of the second conductive layer.

公开(公告)号：US20240195372A1

公开(公告)日：2024-06-13

申请号：US18489140

申请日：2023-10-18

Applicant: Kioxia Corporation

Inventor： Yutaka SHIMIZU ,  Yasuhiro HIRASHIMA ,  Isao FUJISAWA ,  Michael BURGHART ,  Yuanlun ZHANG

IPC: H03F3/45 ,  H10B41/30 ,  H10B43/30

CPC classification number: H03F3/45659 ,  H10B41/30 ,  H10B43/30 ,  H03F2203/45091

Abstract: An amplifier of an input circuit includes: a first PMOS transistor having a gate connected to a first node, a source connected to a second node, and a drain connected to a third node; a second PMOS transistor having a gate connected to a fourth node that inputs a reference signal, a source connected to the second node, and a drain connected to a fifth node; a current source connected between a power supply voltage and the second node; a load circuit connected between the third node and a ground voltage; a first NMOS transistor having a gate connected to the first node, a drain connected to the power supply voltage, and a source connected to the fifth node; and a second NMOS transistor having a gate connected to the fourth node, a drain connected to the power supply voltage, and a source connected to the third node.