公开(公告)号：US12223178B2

公开(公告)日：2025-02-11

申请号：US17939150

申请日：2022-09-07

Applicant: Kioxia Corporation

Inventor： Koichi Nagai ,  Naoki Esaka ,  Toyohide Isshi

IPC: G06F3/06

Abstract: According to one embodiment, an information processing apparatus includes a nonvolatile memory and a CPU. The CPU stores, to the nonvolatile memory, first data, and management data including information equivalent to a write command associated with the first data and designating a first LBA range, and performs a first transmission of the write command to a memory system. When writing of second data to a second LBA range including a third LBA range that is at least a portion of the first LBA range or deallocation of the second LBA range is requested before a second response to the write command is received, the CPU transmits, to the system, a command to cancel writing to at least the third LBA range from writing of the first data to the first LBA range in accordance with the write command.

公开(公告)号：US11899962B2

公开(公告)日：2024-02-13

申请号：US17653393

申请日：2022-03-03

Applicant: Kioxia Corporation

Inventor： Naoki Esaka ,  Koichi Nagai ,  Toyohide Isshi

IPC: G06F3/06

CPC classification number: G06F3/0655 ,  G06F3/0604 ,  G06F3/0679

Abstract: According to one embodiment, an information processing apparatus includes a nonvolatile memory and a CPU. The CPU stores first data in the nonvolatile memory, performs a first transmission of a write request associated with the first data to the memory system, and stores management data including information equivalent to the write request in the nonvolatile memory. In response to receiving a first response to the write request transmitted in the first transmission, the CPU adds, to the management data, information indicating that the first response has been received. The CPU deletes the first data and the management data in response to receiving a second response to the write request transmitted in the first transmission after receiving the first response.