Memory Controller and Method For Controlling Access to a Memory, as Well as System Comprising a Memory Controller
    1.
    发明申请
    Memory Controller and Method For Controlling Access to a Memory, as Well as System Comprising a Memory Controller 审中-公开
    用于控制对存储器的访问的内存控制器和方法以及包含存储器控制器的系统

    公开(公告)号:US20080244135A1

    公开(公告)日:2008-10-02

    申请号:US11913660

    申请日:2006-05-01

    IPC分类号: G06F13/36

    CPC分类号: G06F13/1626

    摘要: In the method for controlling access of a plurality of requestors to a shared memory, the following steps are repeated for successive time-windows: receiving access requests from various requestors (S1), determining a type of access requested by the requests, comparing the requested access type with an access type authorized for a respective time-window according to a back-end schedule, generating a first selection of the incoming requests which have the prescribed access type for the relevant time-window, dynamically selecting one of the requests from the first selection.

    摘要翻译: 在用于控制多个请求者对共享存储器的访问的方法中,针对连续的时间窗口重复以下步骤:从各种请求者接收访问请求(S1),确定请求请求的访问类型, 具有根据后端调度被授权用于相应时间窗口的访问类型的访问类型,生成对于相关时间窗口具有规定的访问类型的传入请求的第一选择,动态地选择来自 第一选择。

    Multi-standard viterbi processor
    2.
    发明授权
    Multi-standard viterbi processor 有权
    多标准维特比处理器

    公开(公告)号:US08904266B2

    公开(公告)日:2014-12-02

    申请号:US12853589

    申请日:2010-08-10

    IPC分类号: H03M13/17 H03M13/00 H03M13/41

    摘要: Various embodiments relate to a multi-standard Viterbi decoder. Based on programmable values for constraint length, generator polynomials, and code rate, the multi-standard Viterbi decoder may adhere to a specific convolutional code standard. At a given time, the multi-standard Viterbi decoder may receive a variety of convolutional codes through a channel and may process them using various forms of the trace back method. Various embodiments include a branch metric unit and path metric unit that include a variety of sub-units that may or may not be active based on the value of the programmable value. Various embodiments also enable the multi-standard Viterbi decoder to handle different forms of convolutional codes, such as tail-biting codes. In some embodiments, the multi-standard Viterbi decoder may also process at least two convolutional codes concurrently.

    摘要翻译: 各种实施例涉及多标准维特比解码器。 基于约束长度,生成多项式和码率的可编程值,多标准维特比解码器可以遵循特定的卷积码标准。 在给定时间,多标准维特比解码器可以通过信道接收各种卷积码,并且可以使用各种形式的追溯方法来处理它们。 各种实施例包括分支度量单位和路径度量单位,其包括可基于可编程值的值而可能或可以不是活动的各种子单元。 各种实施例还使得多标准维特比解码器能够处理不同形式的卷积码,例如尾巴码。 在一些实施例中,多标准维特比解码器也可以同时处理至少两个卷积码。

    MULTI-STANDARD VITERBI PROCESSOR
    3.
    发明申请
    MULTI-STANDARD VITERBI PROCESSOR 有权
    多标准VITERBI处理器

    公开(公告)号:US20120042229A1

    公开(公告)日:2012-02-16

    申请号:US12853589

    申请日:2010-08-10

    IPC分类号: H03M13/03 G06F11/10

    摘要: Various embodiments relate to a multi-standard Viterbi decoder. Based on programmable values for constraint length, generator polynomials, and code rate, the multi-standard Viterbi decoder may adhere to a specific convolutional code standard. At a given time, the multi-standard Viterbi decoder may receive a variety of convolutional codes through a channel and may process them using various forms of the trace back method. Various embodiments include a branch metric unit and path metric unit that include a variety of sub-units that may or may not be active based on the value of the programmable value. Various embodiments also enable the multi-standard Viterbi decoder to handle different forms of convolutional codes, such as tail-biting codes. In some embodiments, the multi-standard Viterbi decoder may also process at least two convolutional codes concurrently.

    摘要翻译: 各种实施例涉及多标准维特比解码器。 基于约束长度,生成多项式和码率的可编程值,多标准维特比解码器可以遵循特定的卷积码标准。 在给定时间,多标准维特比解码器可以通过信道接收各种卷积码,并且可以使用各种形式的追溯方法来处理它们。 各种实施例包括分支度量单位和路径度量单位,其包括可基于可编程值的值而可能或可以不是活动的各种子单元。 各种实施例还使得多标准维特比解码器能够处理不同形式的卷积码,例如尾巴码。 在一些实施例中,多标准维特比解码器也可以同时处理至少两个卷积码。