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公开(公告)号：US20090004796A1
公开(公告)日：2009-01-01
申请号：US12211074
申请日：2008-09-15
IPC分类号： H01L21/336
CPC分类号： H01L27/115 , H01L27/11519 , H01L27/11521
摘要： A method of manufacturing a non-volatile memory includes providing a substrate and forming a patterned mask layer, a tunnel dielectric layer, and a first conductive layer on the substrate. The first conductive layer on the mask layer is removed to form second conductive layers disposed on the sidewall of the mask layer and the substrate. The mask layer is then removed and a source region is formed. Subsequently, an inter-gate dielectric layer and a third conductive layer are formed on the substrate. The third conductive layer is patterned to cover the source region and a portion of the second conductive layer on both sides of the source region. A portion of the inter-gate dielectric layer and the second conductive layers are then removed. After that, a dielectric layer, a fourth conductive layer, and a drain region are formed, respectively.
摘要翻译： 制造非易失性存储器的方法包括提供衬底并在衬底上形成图案化掩模层，隧道介电层和第一导电层。 去除掩模层上的第一导电层以形成布置在掩模层和基板的侧壁上的第二导电层。 然后去除掩模层并形成源区。 随后，在衬底上形成栅极间电介质层和第三导电层。 第三导电层被图案化以覆盖源极区域和源区域两侧上的第二导电层的一部分。 然后去除栅极间电介质层和第二导电层的一部分。 之后，分别形成电介质层，第四导电层和漏极区域。
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公开(公告)号：US07491998B2
公开(公告)日：2009-02-17
申请号：US11536693
申请日：2006-09-29
IPC分类号： H01L29/76
CPC分类号： H01L29/7883 , G11C16/0433 , H01L27/115 , H01L27/11521 , H01L27/11558
摘要： A one time programmable memory including a substrate, a plurality of isolation structures, a first transistor, and a second transistor is provided. The isolation structures are disposed in the substrate for defining an active area. A recess is formed on each of the isolation structures so that the top surface of the isolation structure is lower than that of the substrate. The first transistor is disposed on the active area of the substrate and is extended to the sidewall of the recess. The gate of the first transistor is a select gate. The second transistor is disposed on the active area of the substrate and is connected to the first transistor in series. The gate of the second transistor is a floating gate which is disposed across the substrate between the isolation structures in blocks and is extended to the sidewall of the recess.
摘要翻译： 提供一种包括衬底，多个隔离结构，第一晶体管和第二晶体管的可编程存储器。 隔离结构设置在基板中以限定有效区域。 在每个隔离结构上形成凹部，使得隔离结构的顶表面低于衬底的顶表面。 第一晶体管设置在衬底的有源区上并延伸到凹槽的侧壁。 第一晶体管的栅极是选择栅极。 第二晶体管设置在衬底的有源区上，并串联连接到第一晶体管。 第二晶体管的栅极是浮动栅极，其在块之间的隔离结构之间横跨衬底设置并且延伸到凹部的侧壁。
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公开(公告)号：US20070221980A1
公开(公告)日：2007-09-27
申请号：US11536693
申请日：2006-09-29
IPC分类号： H01L29/76
CPC分类号： H01L29/7883 , G11C16/0433 , H01L27/115 , H01L27/11521 , H01L27/11558
摘要： A one time programmable memory including a substrate, a plurality of isolation structures, a first transistor, and a second transistor is provided. The isolation structures are disposed in the substrate for defining an active area. A recess is formed on each of the isolation structures so that the top surface of the isolation structure is lower than that of the substrate. The first transistor is disposed on the active area of the substrate and is extended to the sidewall of the recess. The gate of the first transistor is a select gate. The second transistor is disposed on the active area of the substrate and is connected to the first transistor in series. The gate of the second transistor is a floating gate which is disposed across the substrate between the isolation structures in blocks and is extended to the sidewall of the recess.
摘要翻译： 提供一种包括衬底，多个隔离结构，第一晶体管和第二晶体管的可编程存储器。 隔离结构设置在基板中以限定有效区域。 在每个隔离结构上形成凹部，使得隔离结构的顶表面低于衬底的顶表面。 第一晶体管设置在衬底的有源区上并延伸到凹槽的侧壁。 第一晶体管的栅极是选择栅极。 第二晶体管设置在衬底的有源区上，并串联连接到第一晶体管。 第二晶体管的栅极是浮动栅极，其在块之间的隔离结构之间横跨衬底设置并且延伸到凹部的侧壁。
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公开(公告)号：US07446370B2
公开(公告)日：2008-11-04
申请号：US11308667
申请日：2006-04-20
IPC分类号： H01L29/788
CPC分类号： H01L27/115 , H01L27/11519 , H01L27/11521
摘要： A non-volatile memory is provided, including a substrate, a control gate, a floating gate, and a select gate. A source region and a drain region are disposed in the substrate. The control gate is disposed on the substrate between the source region and the drain region. The floating gate is disposed between the control gate and the substrate. The cross-section of the floating gate presents, for example, an L-shape and the floating gate includes a central region which is perpendicular to the substrate and a lateral region which is parallel to the substrate. The central region is adjacent to the source region. The select gate is disposed on the sidewall of the control gate and the lateral region of the floating gate, and is adjacent to the drain region. Besides, the present invention further includes a method of manufacturing the above non-volatile memory.
摘要翻译： 提供了一种非易失性存储器，包括基板，控制栅极，浮动栅极和选择栅极。 源极区域和漏极区域设置在衬底中。 控制栅极设置在源极区域和漏极区域之间的衬底上。 浮栅设置在控制栅极和衬底之间。 浮动栅极的横截面呈现例如L形，并且浮动栅极包括垂直于衬底的中心区域和平行于衬底的横向区域。 中心区域与源区域相邻。 选择栅极设置在控制栅极的侧壁和浮置栅极的横向区域上，并且与漏极区域相邻。 此外，本发明还包括制造上述非易失性存储器的方法。
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公开(公告)号：US20070262368A1
公开(公告)日：2007-11-15
申请号：US11308667
申请日：2006-04-20
IPC分类号： H01L29/76
CPC分类号： H01L27/115 , H01L27/11519 , H01L27/11521
摘要： A non-volatile memory is provided, including a substrate, a control gate, a floating gate, and a select gate. A source region and a drain region are disposed in the substrate. The control gate is disposed on the substrate between the source region and the drain region. The floating gate is disposed between the control gate and the substrate. The cross-section of the floating gate presents, for example, an L-shape and the floating gate includes a central region which is perpendicular to the substrate and a lateral region which is parallel to the substrate. The central region is adjacent to the source region. The select gate is disposed on the sidewall of the control gate and the lateral region of the floating gate, and is adjacent to the drain region. Besides, the present invention further includes a method of manufacturing the above non-volatile memory.
摘要翻译： 提供了一种非易失性存储器，包括基板，控制栅极，浮动栅极和选择栅极。 源极区域和漏极区域设置在衬底中。 控制栅极设置在源极区域和漏极区域之间的衬底上。 浮栅设置在控制栅极和衬底之间。 浮动栅极的横截面呈现例如L形，并且浮动栅极包括垂直于衬底的中心区域和平行于衬底的横向区域。 中心区域与源区域相邻。 选择栅极设置在控制栅极的侧壁和浮置栅极的横向区域上，并且与漏极区域相邻。 此外，本发明还包括制造上述非易失性存储器的方法。
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