中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

6 records (took 0.021 seconds)

    On die low power high accuracy reference clock generation
    1.
    发明授权
    On die low power high accuracy reference clock generation 有权
    低功耗高精度基准时钟生成

    公开(公告)号：US08610479B2

    公开(公告)日：2013-12-17

    申请号：US13276269

    申请日：2011-10-18

    Applicant: Kochung Lee ,  Quan Yu ,  Yuntao Zhu ,  Lei Xie ,  Ming Qu

    Inventor： Kochung Lee ,  Quan Yu ,  Yuntao Zhu ,  Lei Xie ,  Ming Qu

    IPC: G06F1/04

    CPC classification number: H03L7/22

    Abstract: A system and method are disclosed for generating a high accuracy and low power on die reference clock. An LC clock is generated on die and a frequency divider lowers the LC clock frequency to a target reference frequency. An RCO clock is generated on die with an unknown initial frequency. The RCO clock and target reference clock are compared to determine in which direction the frequency of the RCO clock should be adjusted to move closer to the target reference frequency. A signal is sent causing a current source or capacitor in the RCO circuit to be modified. Therefore, the RCO clock frequency is adjusted. The RCO circuit is repeatedly adjusted until the RCO clock frequency is sufficiently accurate. The LC clock is disabled to conserve the power that would have been consumed in generating the LC clock.

    Abstract translation: 公开了一种用于在芯片参考时钟上产生高精度和低功耗的系统和方法。 在芯片上产生LC时钟，分频器将LC时钟频率降低到目标参考频率。 在未知的初始频率的芯片上产生RCO时钟。 比较RCO时钟和目标参考时钟，确定在哪个方向上调整RCO时钟的频率以更接近目标参考频率。 发送信号，导致RCO电路中的电流源或电容器被修改。 因此，调整RCO时钟频率。 RCO电路重复调整，直到RCO时钟频率足够准确。 LC时钟被禁用，以节省在生成LC时钟时消耗的功率。

    ON DIE LOW POWER HIGH ACCURACY REFERENCE CLOCK GENERATION
    2.
    发明申请
    ON DIE LOW POWER HIGH ACCURACY REFERENCE CLOCK GENERATION 有权
    ON DIE低功率高精度参考时钟产生

    公开(公告)号：US20130093466A1

    公开(公告)日：2013-04-18

    申请号：US13276269

    申请日：2011-10-18

    Applicant: Kochung Lee ,  Quan Yu ,  Yuntao Zhu ,  Lei Xie ,  Ming Qu

    Inventor： Kochung Lee ,  Quan Yu ,  Yuntao Zhu ,  Lei Xie ,  Ming Qu

    IPC: H03D13/00

    CPC classification number: H03L7/22

    Abstract: A system and method are disclosed for generating a high accuracy and low power on die reference clock. An LC clock is generated on die and a frequency divider lowers the LC clock frequency to a target reference frequency. An RCO clock is generated on die with an unknown initial frequency. The RCO clock and target reference clock are compared to determine in which direction the frequency of the RCO clock should be adjusted to move closer to the target reference frequency. A signal is sent causing a current source or capacitor in the RCO circuit to be modified. Therefore, the RCO clock frequency is adjusted. The RCO circuit is repeatedly adjusted until the RCO clock frequency is sufficiently accurate. The LC clock is disabled to conserve the power that would have been consumed in generating the LC clock.

    Abstract translation: 公开了一种用于在芯片参考时钟上产生高精度和低功耗的系统和方法。 在芯片上产生LC时钟，分频器将LC时钟频率降低到目标参考频率。 在未知的初始频率的芯片上产生RCO时钟。 比较RCO时钟和目标参考时钟，确定在哪个方向上调整RCO时钟的频率以更接近目标参考频率。 发送信号，导致RCO电路中的电流源或电容器被修改。 因此，调整RCO时钟频率。 RCO电路重复调整，直到RCO时钟频率足够准确。 LC时钟被禁用，以节省在生成LC时钟时消耗的功率。

    On die jitter tolerance test
    3.
    发明授权
    On die jitter tolerance test 有权
    裸片抖动容限测试

    公开(公告)号：US08923375B2

    公开(公告)日：2014-12-30

    申请号：US13538930

    申请日：2012-06-29

    Applicant: Ming Qu ,  Yuanping Chen ,  Yuntao Zhu ,  Quan Yu ,  Kochung Lee

    Inventor： Ming Qu ,  Yuanping Chen ,  Yuntao Zhu ,  Quan Yu ,  Kochung Lee

    IPC: H04B17/00

    CPC classification number: H03L7/087 ,  G01R29/26 ,  H03L7/0807 ,  H03L7/081 ,  H03L7/0998 ,  H04B17/104 ,  H04L1/205 ,  H04L1/243 ,  H04L7/033

    Abstract: A system and method are disclosed for performing on die jitter tolerance testing. A set of clocks are generated based on an input signal. The set of clocks include in an in-phase signal based on the data switching edge of the input signal. Additionally, the set of clocks include an inverted clock phase shifted by 180 degrees, and a pair of clocks phase shifted positively and negatively by a certain number of degrees, θ. Data input is sampled based on the inverted clock and the two phase shifted clocks. The eye opening of the input signal can be determined based on whether each of the inverted clock and the two phase shifted clocks sample the correct data from the input signal at various θ values.

    Abstract translation: 公开了一种用于执行裸片抖动容限测试的系统和方法。 基于输入信号产生一组时钟。 该组时钟包括基于输入信号的数据切换沿的同相信号。 此外，该组时钟包括一个偏移180度的反相时钟相位和一对相位正负偏移一定数量的时钟。 基于反相时钟和两个相移时钟对数据输入进行采样。 输入信号的开眼可以基于​​每个反相时钟和两个相移时钟从各种输入信号中的输入信号中得到正确的数据来确定; 价值观。

    On Die Jitter Tolerance Test
    4.
    发明申请
    On Die Jitter Tolerance Test 有权
    关于死机容忍测试

    公开(公告)号：US20140003480A1

    公开(公告)日：2014-01-02

    申请号：US13538930

    申请日：2012-06-29

    Applicant: Ming Qu ,  Yuanping Chen ,  Yuntao Zhu ,  Quan Yu ,  Kochung Lee

    Inventor： Ming Qu ,  Yuanping Chen ,  Yuntao Zhu ,  Quan Yu ,  Kochung Lee

    IPC: H04B17/00

    CPC classification number: H03L7/087 ,  G01R29/26 ,  H03L7/0807 ,  H03L7/081 ,  H03L7/0998 ,  H04B17/104 ,  H04L1/205 ,  H04L1/243 ,  H04L7/033

    Abstract: A system and method are disclosed for performing on die jitter tolerance testing. A set of clocks are generated based on an input signal. The set of clocks include in an in-phase signal based on the data switching edge of the input signal. Additionally, the set of clocks include an inverted clock phase shifted by 180 degrees, and a pair of clocks phase shifted positively and negatively by a certain number of degrees, θ. Data input is sampled based on the inverted clock and the two phase shifted clocks. The eye opening of the input signal can be determined based on whether each of the inverted clock and the two phase shifted clocks sample the correct data from the input signal at various θ values.

    Abstract translation: 公开了一种用于执行裸片抖动容限测试的系统和方法。 基于输入信号产生一组时钟。 该组时钟包括基于输入信号的数据切换沿的同相信号。 此外，该组时钟包括偏移180度的反相时钟相位和一对相位偏移一定数量度θ的时钟。 基于反相时钟和两个相移时钟对数据输入进行采样。 可以基于反相时钟和两个相移时钟中的每一个是否以各种θ值从输入信号中采样正确的数据来确定输入信号的开眼。

    Active antenna, base station, method for refreshing amplitudes and phases, and method for processing signals
    5.
    发明授权
    Active antenna, base station, method for refreshing amplitudes and phases, and method for processing signals 有权
    有源天线，基站，振幅和相位刷新方法以及处理信号的方法

    公开(公告)号：US08391377B2

    公开(公告)日：2013-03-05

    申请号：US13026914

    申请日：2011-02-14

    Applicant: Yuanrong Zhu ,  Jianjun Chen ,  Zhubiao He ,  Jianfeng Wu ,  Ming Xu ,  Yi Zhang ,  Yuntao Zhu ,  Pinghua He

    Inventor： Yuanrong Zhu ,  Jianjun Chen ,  Zhubiao He ,  Jianfeng Wu ,  Ming Xu ,  Yi Zhang ,  Yuntao Zhu ,  Pinghua He

    IPC: H04L27/00

    CPC classification number: H01Q1/246 ,  H01Q3/267 ,  H01Q3/34 ,  H04B7/0617 ,  H04B7/0842 ,  H04B17/11 ,  H04B17/21

    Abstract: An active antenna, a base station, a method for refreshing the amplitude and phase, and a signal processing method are disclosed to simplify the structure of a phase shifter and guarantee the reliability of the phase shifter. The active antenna or the base station includes an antenna dipole array, a transceiver array, a digital processing unit (DPU), and a transceiving calibration unit. During signal reception, the transceiver demodulates a radio frequency (RF) signal of the antenna dipole into an IQ analog signal, and outputs the IQ analog signal to the DPU; the DPU converts the demodulated IQ analog signal into an IQ digital signal, and performs digital beam forming (DBF) on the IQ digital signal according to the transceiving calibration unit; during signal transmission, the transceiver modulates the IQ analog signal of the DPU into an RF signal, and outputs the RF signal to the antenna dipole; the DPU converts a signal of a base band unit (BBU) into an IQ digital signal in serial/parallel (S/P) mode, and performs DBF on the IQ digital signal according to the transceiving calibration unit.

    Abstract translation: 公开了有源天线，基站，振幅和相位刷新的方法以及信号处理方法，以简化移相器的结构并保证移相器的可靠性。 有源天线或基站包括天线偶极子阵列，收发器阵列，数字处理单元（DPU）和收发校准单元。 在信号接收期间，收发器将天线偶极子的射频（RF）信号解调为IQ模拟信号，并将IQ模拟信号输出到DPU; DPU将解调的IQ模拟信号转换为IQ数字信号，并根据收发校准单元对IQ数字信号进行数字波束形成（DBF）; 在信号传输期间，收发器将DPU的IQ模拟信号调制成RF信号，并将RF信号输出到天线偶极子; DPU将基带单元（BBU）的信号以串行/并行（S / P）模式转换为IQ数字信号，并根据收发校准单元对IQ数字信号执行DBF。

Patent Agency Ranking