公开(公告)号：US08269284B2

公开(公告)日：2012-09-18

申请号：US13019600

申请日：2011-02-02

申请人： Koji Nil ,  Motoshige Igarashi

发明人： Koji Nil ,  Motoshige Igarashi

IPC分类号： H01L27/088 ,  H01L21/8234

CPC分类号： H01L21/823412 ,  H01L27/11 ,  H01L27/1104

摘要： There are provided a method of manufacturing a semiconductor device which achieves a reduction in implantation masks, and such a semiconductor device. By implanting boron into NMOS regions using a resist mask and another resist mask as the implantation masks, p-type impurity regions serving as the halo regions of access transistors and drive transistors are formed. By further implanting phosphorus or arsenic into a PMOS region using another resist mask as the implantation mask, n-type impurity regions serving as the halo regions of load transistors are formed.

摘要翻译： 提供了一种制造半导体器件的方法，其实现了注入掩模的减少以及这种半导体器件。 通过使用抗蚀剂掩模和另一抗蚀剂掩模将硼注入NMOS区域作为注入掩模，形成用作存取晶体管和驱动晶体管的晕区的p型杂质区。 通过使用另一抗蚀剂掩模作为注入掩模将磷或砷进一步注入PMOS区，形成用作负载晶体管的晕区的n型杂质区。