公开(公告)号：US08269284B2

公开(公告)日：2012-09-18

申请号：US13019600

申请日：2011-02-02

申请人： Koji Nil ,  Motoshige Igarashi

发明人： Koji Nil ,  Motoshige Igarashi

IPC分类号： H01L27/088 ,  H01L21/8234

CPC分类号： H01L21/823412 ,  H01L27/11 ,  H01L27/1104

摘要： There are provided a method of manufacturing a semiconductor device which achieves a reduction in implantation masks, and such a semiconductor device. By implanting boron into NMOS regions using a resist mask and another resist mask as the implantation masks, p-type impurity regions serving as the halo regions of access transistors and drive transistors are formed. By further implanting phosphorus or arsenic into a PMOS region using another resist mask as the implantation mask, n-type impurity regions serving as the halo regions of load transistors are formed.

摘要翻译： 提供了一种制造半导体器件的方法，其实现了注入掩模的减少以及这种半导体器件。 通过使用抗蚀剂掩模和另一抗蚀剂掩模将硼注入NMOS区域作为注入掩模，形成用作存取晶体管和驱动晶体管的晕区的p型杂质区。 通过使用另一抗蚀剂掩模作为注入掩模将磷或砷进一步注入PMOS区，形成用作负载晶体管的晕区的n型杂质区。

公开(公告)号：US20110193173A1

公开(公告)日：2011-08-11

申请号：US13019600

申请日：2011-02-02

申请人： Koji NII ,  Motoshige Igarashi

发明人： Koji NII ,  Motoshige Igarashi

IPC分类号： H01L27/088 ,  H01L21/8234

CPC分类号： H01L21/823412 ,  H01L27/11 ,  H01L27/1104

摘要： There are provided a method of manufacturing a semiconductor device which achieves a reduction in implantation masks, and such a semiconductor device. By implanting boron into NMOS regions using a resist mask and another resist mask as the implantation masks, p-type impurity regions serving as the halo regions of access transistors and drive transistors are formed. By further implanting phosphorus or arsenic into a PMOS region using another resist mask as the implantation mask, n-type impurity regions serving as the halo regions of load transistors are formed.

摘要翻译： 提供了一种制造半导体器件的方法，其实现了注入掩模的减少以及这种半导体器件。 通过使用抗蚀剂掩模和另一抗蚀剂掩模将硼注入NMOS区域作为注入掩模，形成用作存取晶体管和驱动晶体管的晕区的p型杂质区。 通过使用另一抗蚀剂掩模作为注入掩模将磷或砷进一步注入PMOS区，形成用作负载晶体管的晕区的n型杂质区。

公开(公告)号：US20100093145A1

公开(公告)日：2010-04-15

申请号：US12636408

申请日：2009-12-11

申请人： Nobuo TSUBOI ,  Motoshige Igarashi

发明人： Nobuo TSUBOI ,  Motoshige Igarashi

IPC分类号： H01L21/8239

CPC分类号： H01L27/1104 ,  H01L27/11

摘要： A structure is adopted for a layout of an SRAM cell which provides a local wiring 3a between a gate 2a and gate 2b and connects an active region 1a and an active region 1b. This eliminates the necessity for providing a contact between the gate 2a and the gate 2b. Therefore, it is possible to reduce the size of a memory cell region C in a short side direction. Furthermore, a structure whereby a left end of a gate 2c is retreated from the gate 2a and a local wiring 3b which connects the active region 1b and gate 2c disposed in a diagonal direction is adopted. This allows the gate 2a to be shifted toward the center of the memory cell region C.

摘要翻译： 采用在栅极2a和栅极2b之间提供局部布线3a并连接有源区域1a和有源区域1b的SRAM单元布局的结构。 这消除了在栅极2a和栅极2b之间提供接触的必要性。 因此，可以在短边方向上减小存储单元区域C的尺寸。 此外，采用栅极2c的左端从栅极2a退出的结构和连接沿对角线方向设置的有源区域1b和栅极2c的局部布线3b。 这允许栅极2a朝向存储单元区域C的中心移动。

公开(公告)号：US06683351B2

公开(公告)日：2004-01-27

申请号：US10225128

申请日：2002-08-22

申请人： Kiyoaki Morita ,  Motoshige Igarashi

发明人： Kiyoaki Morita ,  Motoshige Igarashi

IPC分类号： H01L2362

CPC分类号： H01L27/0629 ,  H01L23/485 ,  H01L27/088 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device restricting the antenna effect without complicating the manufacturing process and a manufacturing method of such a semiconductor device are provided. In addition, a semiconductor device ensuring matching or equality in characteristics of pairing transistors and a manufacturing method of such a semiconductor device are provided. The semiconductor device includes an interconnection that is placed on an insulating film covering a gate electrode and a semiconductor substrate and is electrically connected to the gate electrode. The semiconductor device also includes a dummy transistor that is formed on the semiconductor substrate and is unprovided with an interconnection required for a transistor. The interconnection is electrically connected to a source/drain region of the dummy transistor.

摘要翻译： 提供限制天线效应而不使制造工艺复杂化的半导体器件和这种半导体器件的制造方法。 此外，提供确保配对晶体管的特性匹配或相等的半导体器件以及这种半导体器件的制造方法。 半导体器件包括布置在覆盖栅电极和半导体衬底的绝缘膜上并且与栅电极电连接的互连。 半导体器件还包括形成在半导体衬底上的虚拟晶体管，并且未提供晶体管所需的互连。 互连电连接到虚拟晶体管的源/漏区。

公开(公告)号：US20050062099A1

公开(公告)日：2005-03-24

申请号：US10981537

申请日：2004-11-05

申请人： Kenji Yoshiyama ,  Motoshige Igarashi ,  Keiichi Yamada ,  Katsuya Okada ,  Keiichi Higashitani

发明人： Kenji Yoshiyama ,  Motoshige Igarashi ,  Keiichi Yamada ,  Katsuya Okada ,  Keiichi Higashitani

IPC分类号： H01L21/336 ,  H01L21/28 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/78 ,  H01L29/792

CPC分类号： H01L29/6656 ,  H01L21/28247 ,  H01L21/823462 ,  H01L21/823468

摘要： A semiconductor device and a manufacturing method thereof permitting the quality of gate insulating films to be prevented from deteriorating and thereby permitting electrical characteristics of the device to be prevented from deteriorating are provided. In a semiconductor device including a plurality of field effect transistors, an oxidation protection film 21 is formed on a side of one gate electrode 19.

摘要翻译： 提供一种半导体器件及其制造方法，其能够防止栅绝缘膜的质量恶化，从而防止器件的电特性劣化。 在包括多个场效应晶体管的半导体器件中，在一个栅电极19的一侧形成氧化保护膜21。

公开(公告)号：US06853030B2

公开(公告)日：2005-02-08

申请号：US10370762

申请日：2003-02-24

申请人： Kenji Yoshiyama ,  Motoshige Igarashi ,  Keiichi Yamada ,  Katsuya Okada ,  Keiichi Higashitani

发明人： Kenji Yoshiyama ,  Motoshige Igarashi ,  Keiichi Yamada ,  Katsuya Okada ,  Keiichi Higashitani

IPC分类号： H01L21/336 ,  H01L21/28 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/78 ,  H01L29/788 ,  H01L27/01 ,  H01L27/12 ,  H01L29/76 ,  H01L29/94

CPC分类号： H01L29/6656 ,  H01L21/28247 ,  H01L21/823462 ,  H01L21/823468

摘要： A semiconductor device and a manufacturing method thereof permitting the quality of gate insulating films to be prevented from deteriorating and thereby permitting electrical characteristics of the device to be prevented from deteriorating are provided. In a semiconductor device including a plurality of field effect transistors, an oxidation protection film 21 is formed on a side of one gate electrode 19.

摘要翻译： 提供一种半导体器件及其制造方法，其能够防止栅绝缘膜的质量恶化，从而防止器件的电特性劣化。 在包括多个场效应晶体管的半导体器件中，在一个栅电极19的一侧形成氧化保护膜21。

公开(公告)号：US06838777B2

公开(公告)日：2005-01-04

申请号：US10648223

申请日：2003-08-27

申请人： Motoshige Igarashi

发明人： Motoshige Igarashi

IPC分类号： H01L21/336 ,  H01L21/28 ,  H01L21/8234 ,  H01L29/423 ,  H01L29/78 ,  H01L27/088

CPC分类号： H01L29/6656 ,  H01L21/28114 ,  H01L21/823456 ,  H01L21/823468 ,  H01L22/12 ,  H01L22/20 ,  H01L29/42376 ,  H01L29/7833 ,  Y10S257/90

摘要： Gate electrodes (3) are formed on a semiconductor substrate (1), each with a gate insulating film (2) interposed therebetween. A pair of offset spacers (4) are respectively formed on opposite side faces of each of the gate insulating film (2) and the gate electrodes (3). Diffusion layers (5) are formed in the semiconductor substrate (1) on opposite sides of a portion of the semiconductor substrate (1) immediately under each of the gate electrodes (3), by ion implantation. While the gate electrodes (3) have various configurations such as a gate electrode having a rectangular section, an upwardly tapered gate electrode and a downwardly tapered gate electrode, respective configurations of the offset spacers (4) are adjusted so that lengths each obtained by adding the gate length of the gate electrode (3), which gate length extends on an interface between the gate insulating film (2) and the gate electrode (3), to a width of the pair of the offset spacers (4), which width extends on an interface between the offset spacers (4) and the semiconductor substrate (1), are substantially uniform.

摘要翻译： 在半导体基板（1）上形成有栅电极（3），每个栅极电极（3）均插入有栅极绝缘膜（2）。 在栅极绝缘膜（2）和栅电极（3）的相对侧面分别形成有一对偏置间隔物（4）。 通过离子注入在半导体衬底（1）内的半导体衬底（1）的每个栅电极（3）的正下方的相对侧的相对侧上的半导体衬底（1）中形成扩散层（5）。 虽然栅电极（3）具有各种结构，例如具有矩形截面的栅电极，向上锥形的栅电极和向下锥形的栅电极，但是调整偏置间隔物（4）的各个配置，使得通过添加 栅极电极（3）的栅极长度在栅极绝缘膜（2）和栅电极（3）之间的界面上延伸的栅极长度相对于一对偏移间隔物（4）的宽度，宽度 在偏置间隔物（4）和半导体衬底（1）之间的界面上延伸，基本均匀。

公开(公告)号：US06835647B2

公开(公告)日：2004-12-28

申请号：US10382902

申请日：2003-03-07

申请人： Hiroyuki Amishiro ,  Motoshige Igarashi

发明人： Hiroyuki Amishiro ,  Motoshige Igarashi

IPC分类号： H01L214763

CPC分类号： H01L23/5283 ,  H01L23/5222 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device including an interconnection structure having superior electrical characteristics and allowing higher speed of operation and lower power consumption even when miniaturized, manufacturing method thereof and a method of designing a semiconductor circuit used in the manufacturing method are provided. In the semiconductor device, a conductive region is formed on a main surface of a semiconductor substrate. A first interconnection layer is electrically connected to the conductive region, has a relatively short line length, and contains a material having relatively high electrical resistance. A first insulator is formed to surround the first interconnection layer and has a relatively low dielectric constant. A second interconnection layer is formed on the main surface of the semiconductor substrate, contains a material having low electrical resistance than the material contained in the first interconnection layer, and has longer line length than the first interconnection layer. A second insulator is formed to surround the second interconnection layer and has a dielectric constant higher than the first insulator.

摘要翻译： 提供一种包括具有优异的电气特性并且即使当其小型化也允许更高的操作速度和更低的功率消耗的互连结构的半导体器件，并且提供了制造方法中使用的半导体电路的设计方法。 在半导体器件中，在半导体衬底的主表面上形成导电区域。 第一互连层电连接到导电区域，具有相对短的线路长度，并且包含具有相对较高电阻的材料。 形成第一绝缘体以包围第一互连层并且具有相对低的介电常数。 第二互连层形成在半导体衬底的主表面上，包含比第一互连层中包含的材料低的电阻，并且具有比第一互连层更长的线长度。 形成第二绝缘体以包围第二互连层并且具有高于第一绝缘体的介电常数。

公开(公告)号：US06720626B1

公开(公告)日：2004-04-13

申请号：US09115250

申请日：1998-07-14

申请人： Motoshige Igarashi

发明人： Motoshige Igarashi

IPC分类号： H01L2976

CPC分类号： H01L29/4925 ,  H01L21/26506 ,  H01L21/26586 ,  H01L21/28035 ,  H01L21/823842 ,  H01L29/4916 ,  H01L29/665 ,  H01L29/6653

摘要： A gate insulating film is formed on a semiconductor substrate, and a gate electrode is formed by deposition of semiconductor material on the gate insulating film. An amorphous layer is then formed along the surface of or inside the gate electrode, and side walls are formed on the gate electrode. Finally, impurities are implanted into the semiconductor substrate by ion implantation while the gate electrode and the side walls are used as masks.

摘要翻译： 在半导体衬底上形成栅极绝缘膜，并且通过在栅极绝缘膜上沉积半导体材料形成栅电极。 然后沿着栅电极的表面或内部形成非晶层，并且在栅电极上形成侧壁。 最后，通过离子注入将杂质注入到半导体衬底中，同时将栅电极和侧壁用作掩模。

公开(公告)号：US6165878A

公开(公告)日：2000-12-26

申请号：US221128

申请日：1998-12-28

申请人： Hideyo Haruhana ,  Keiichi Higashitani ,  Motoshige Igarashi ,  Masao Sugiyama

发明人： Hideyo Haruhana ,  Keiichi Higashitani ,  Motoshige Igarashi ,  Masao Sugiyama

IPC分类号： H01L21/28 ,  H01L21/027 ,  H01L21/31 ,  H01L21/336 ,  H01L21/60 ,  H01L21/768 ,  H01L29/78 ,  H01L21/3205 ,  H01L21/4763

CPC分类号： H01L21/76897 ,  H01L21/027 ,  H01L21/76819 ,  H01L21/76829 ,  H01L21/76832

摘要： A method of manufacturing a semiconductor device which prevents a short circuit between a gate electrode and a diffusion layer region if a contact hole is shifted from its proper position. A material having an etch selectivity to an interlayer insulation film is formed over the gate electrode to serve as a cover against the formation of a contact hole. A material is not formed over an interconnect line which is required to be exposed to a contact hole.

摘要翻译： 一种制造半导体器件的方法，如果接触孔从其正确的位置偏移，则可以防止栅电极和扩散层区域之间的短路。 在栅电极上形成具有对层间绝缘膜的蚀刻选择性的材料，以作为防止形成接触孔的盖。 不需要在暴露于接触孔的互连线上形成材料。