公开(公告)号：US20230011215A1

公开(公告)日：2023-01-12

申请号：US17825574

申请日：2022-05-26

Applicant: Korea University Research and Business Foundation

Inventor： Hyung-Min LEE ,  Minil KANG ,  Min-Seong UM

IPC: G06N3/063

Abstract: Provided is a neuromorphic circuit including an input module configured to generate an input voltage, an output module configured to measure a current transmitted from the input module and generate an output voltage, synapse modules configured to electrically connect the input module and the output module and determine a current to be transmitted to the output module and including a memory element to which a weight is assigned, and a crossing module configured to control a direction of current flowing through the synapse modules.

公开(公告)号：US20230041306A1

公开(公告)日：2023-02-09

申请号：US17851696

申请日：2022-06-28

Applicant: Korea University Research and Business Foundation

Inventor： Hyung-Min LEE ,  Minil KANG ,  Min-Seong UM

IPC: G11C27/00 ,  G06N3/063

Abstract: An error compensation circuit for analog capacitor memory circuits includes a first transistor and a second transistor with gates connected respectively to top and bottom of an analog memory capacitor to read a voltage charged in the analog memory capacitor; a first switch and a second switch connected respectively to the first transistor and the second transistor to select the voltage to read; a first capacitor and a second capacitor to charge an electric charge to compensate or refresh the analog memory capacitor according to on/off of the first switch and the second switch; and an input terminal connected to sources of the first transistor and the second transistor to apply the voltage to operate the circuit. Accordingly, it is possible to compensate for an unintended phenomenon of the analog capacitor memory or refresh a change in memory value caused by leakage.