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1.发明授权Frequency detection circuit and detection method for clock data recovery circuit 有权时钟数据恢复电路的频率检测电路和检测方法公开(公告)号：US07764088B2
公开(公告)日：2010-07-27
申请号：US12237025
申请日：2008-09-24
IPC分类号： H03D13/00
CPC分类号： H03L7/087 , H03L7/0807 , H03L7/085 , H03L7/089
摘要： A frequency detection circuit and a detection method thereof suitable for a clock data recovery (CDR) circuit are provided. The frequency detection circuit includes a phase detector, a first delayer, a frequency detector, and a logic circuit. The phase detector samples a data signal according to a first clock signal provided by the CDR circuit and provides a phase instruction signal according to the sampling. The first delayer delays the first clock signal to obtain a second clock signal. The frequency detector samples the data signal according to the second clock signal and provides a frequency instruction signal according to the sampling. The logic circuit generates a clock instruction signal according to the phase instruction signal and the frequency instruction signal. The CDR circuit adjusts the frequency of the first clock signal according to the status of the clock instruction signal.
摘要翻译： 提供适用于时钟数据恢复（CDR）电路的频率检测电路及其检测方法。 频率检测电路包括相位检测器，第一延迟器，频率检测器和逻辑电路。 相位检测器根据由CDR电路提供的第一时钟信号对数据信号进行采样，并根据采样提供相位指令信号。 第一延迟器延迟第一时钟信号以获得第二时钟信号。 频率检测器根据第二时钟信号对数据信号进行采样，并根据采样提供频率指令信号。 逻辑电路根据相位指令信号和频率指令信号生成时钟指令信号。 CDR电路根据时钟指令信号的状态来调整第一时钟信号的频率。
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2.发明申请FREQUENCY DETECTION CIRCUIT AND DETECTION METHOD FOR CLOCK DATA RECOVERY CIRCUIT 有权频率检测电路和时钟数据恢复电路的检测方法公开(公告)号：US20100073045A1
公开(公告)日：2010-03-25
申请号：US12237025
申请日：2008-09-24
IPC分类号： H03L7/06
CPC分类号： H03L7/087 , H03L7/0807 , H03L7/085 , H03L7/089
摘要： A frequency detection circuit and a detection method thereof suitable for a clock data recovery (CDR) circuit are provided. The frequency detection circuit includes a phase detector, a first delayer, a frequency detector, and a logic circuit. The phase detector samples a data signal according to a first clock signal provided by the CDR circuit and provides a phase instruction signal according to the sampling. The first delayer delays the first clock signal to obtain a second clock signal. The frequency detector samples the data signal according to the second clock signal and provides a frequency instruction signal according to the sampling. The logic circuit generates a clock instruction signal according to the phase instruction signal and the frequency instruction signal. The CDR circuit adjusts the frequency of the first clock signal according to the status of the clock instruction signal.
摘要翻译： 提供适用于时钟数据恢复（CDR）电路的频率检测电路及其检测方法。 频率检测电路包括相位检测器，第一延迟器，频率检测器和逻辑电路。 相位检测器根据由CDR电路提供的第一时钟信号对数据信号进行采样，并根据采样提供相位指令信号。 第一延迟器延迟第一时钟信号以获得第二时钟信号。 频率检测器根据第二时钟信号对数据信号进行采样，并根据采样提供频率指令信号。 逻辑电路根据相位指令信号和频率指令信号生成时钟指令信号。 CDR电路根据时钟指令信号的状态来调整第一时钟信号的频率。
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