公开(公告)号：US20070224795A1

公开(公告)日：2007-09-27

申请号：US11457032

申请日：2006-07-12

申请人： Kuei Shun CHEN ,  Chin-Hsiang LIN ,  Vencent CHANG ,  Lawrence LIN ,  Lai Chien WEN ,  Jhun Hua CHEN

发明人： Kuei Shun CHEN ,  Chin-Hsiang LIN ,  Vencent CHANG ,  Lawrence LIN ,  Lai Chien WEN ,  Jhun Hua CHEN

IPC分类号： H01L21/44

CPC分类号： H01L21/76811 ,  H01L21/76807 ,  H01L21/76813 ,  H01L21/7684 ,  H01L23/522 ,  H01L23/5226 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method of making an integrated circuit includes providing a low-k dielectric layer on a substrate, the low-k dielectric layer including or adjacent to a plurality of conductive features; patterning the low-k dielectric layer to form trenches; patterning the low-k dielectric layer to form conductive vias and dummy vias, wherein each of the conductive vias is aligned with at least one of the plurality of the conductive features and at least one of the trenches, and each of the dummy vias is a distance above the plurality of conductive features; filling the trenches, conductive vias, and dummy vias using one or more conductive materials; and planarizing the conductive material(s).

摘要翻译： 制造集成电路的方法包括在衬底上提供低k电介质层，低k电介质层包括或邻近多个导电特征; 图案化低k电介质层以形成沟槽; 图案化低k电介质层以形成导电通孔和虚拟通孔，其中每个导电通孔与多个导电特征中的至少一个对齐，并且至少一个沟槽，并且每个虚拟通孔是 在多个导电特征之上的距离; 使用一种或多种导电材料填充沟槽，导电通孔和虚拟通孔; 并平坦化导电材料。