Flexible electronic device and manufacturing method therefor

    公开(公告)号:US11119536B2

    公开(公告)日:2021-09-14

    申请号:US15778481

    申请日:2017-03-09

    Abstract: Provided are a flexible electronic device and a manufacturing method thereof. The flexible electronic device (200) comprises a flexible substrate (210) and a device layer formed on the flexible substrate (210). The device layer comprises a semiconductor structure (220) and a wire structure (230) connected to the semiconductor structure, the wire structure (230) having an extension direction same to a channel direction of the semiconductor structure (220). The extension direction of the first wire structure (230) forms an included angle smaller than 90° with respect to a stretching direction of the flexible substrate (210). In the flexible electronic device (200) and manufacturing method thereof of the present invention, the channel direction of the semiconductor structure (220) and the extension direction of the first wire structure (230) are adjusted, such that the semiconductor structure (220) and the first wire structure (230) are least affected by a stress, thus ensuring electrical property and flexibility of the flexible electronic device (200).

    Pixel arrangement structure, display panel and display apparatus

    公开(公告)号:US11114016B2

    公开(公告)日:2021-09-07

    申请号:US17011212

    申请日:2020-09-03

    Abstract: Provided are a pixel arrangement structure, a display panel, and a display apparatus. The pixel arrangement structure includes a plurality of first sub-pixels, a plurality of second sub-pixels, and a plurality of third sub-pixels, and the plurality of first, second and third sub-pixels form a plurality of virtual polygons. In each virtual polygon, the second sub-pixels and the third sub-pixels are located at a first vertex and a second vertex of the virtual polygon, respectively, the first vertex and the second vertex are alternated and spaced apart from each other, the first sub-pixel is located inside the virtual polygon, a first distance from a center of the first sub-pixel to a center of any third sub-pixel is equal, a second distance from a center of the first sub-pixel to a center of any second sub-pixel is equal, and the first distance is equal to the second distance.

    THIN FILM TRANSISTOR AND PREPARATION METHOD THEREOF

    公开(公告)号:US20180097119A1

    公开(公告)日:2018-04-05

    申请号:US15830423

    申请日:2017-12-04

    Abstract: A thin film transistor and a preparation method thereof are provided. The thin film transistor includes an upper gate electrode, a lower gate electrode, an upper insulating layer, a lower insulating layer, a semiconductor layer, a source electrode and a drain electrode. The lower insulating layer is arranged on the lower gate electrode, the semiconductor layer is arranged on the lower insulating layer, the semiconductor layer is respectively lapped with the source electrode and the drain electrode, the upper insulating layer covers the semiconductor layer, and the upper gate electrode is arranged on the upper insulating layer. In a plane parallel to a conducting channel, there is a first gap between an orthographic projection of the upper gate electrode and an orthographic projection of the source electrode, and there is a second gap between the orthographic projection of the upper gate electrode and an orthographic projection of the drain electrode.

    Thin film transistor
    9.
    发明授权

    公开(公告)号:US10665725B2

    公开(公告)日:2020-05-26

    申请号:US15830423

    申请日:2017-12-04

    Abstract: A thin film transistor and a preparation method thereof are provided. The thin film transistor includes an upper gate electrode, a lower gate electrode, an upper insulating layer, a lower insulating layer, a semiconductor layer, a source electrode and a drain electrode. The lower insulating layer is arranged on the lower gate electrode, the semiconductor layer is arranged on the lower insulating layer, the semiconductor layer is respectively lapped with the source electrode and the drain electrode, the upper insulating layer covers the semiconductor layer, and the upper gate electrode is arranged on the upper insulating layer. In a plane parallel to a conducting channel, there is a first gap between an orthographic projection of the upper gate electrode and an orthographic projection of the source electrode, and there is a second gap between the orthographic projection of the upper gate electrode and an orthographic projection of the drain electrode.

Patent Agency Ranking