公开(公告)号：US20060289935A1

公开(公告)日：2006-12-28

申请号：US11512850

申请日：2006-08-29

申请人： Kuo-Feng Yu ,  Jian-Hsing Lee ,  Yi-Hsun Wu ,  C.S Tang

发明人： Kuo-Feng Yu ,  Jian-Hsing Lee ,  Yi-Hsun Wu ,  C.S Tang

IPC分类号： H01L23/62

CPC分类号： H01L27/0266

摘要： A layout structure for an ESD protection circuit includes a first MOS device area having a first and second doped regions of the same polarity disposed at two sides of a first conductive gate layer, and a third doped region disposed along the first doped region at one side of the first conductive gate layer. The third doped region has a polarity different from that of the first and second doped regions, such that the third doped region and the second doped region form a diode for enhancing dissipation of ESD current during a negative ESD event.

摘要翻译： ESD保护电路的布局结构包括：第一MOS器件区域，具有设置在第一导电栅极层的两侧的具有相同极性的第一和第二掺杂区域;以及第三掺杂区域，沿第一掺杂区域设置在一侧 的第一导电栅极层。 第三掺杂区域具有与第一和第二掺杂区域不同的极性，使得第三掺杂区域和第二掺杂区域形成用于在负ESD事件期间增强ESD电流的耗散的二极管。

公开(公告)号：US07465994B2

公开(公告)日：2008-12-16

申请号：US11512850

申请日：2006-08-29

申请人： Kuo-Feng Yu ,  Jian-Hsing Lee ,  Yi-Hsun Wu ,  C.S Tang

发明人： Kuo-Feng Yu ,  Jian-Hsing Lee ,  Yi-Hsun Wu ,  C.S Tang

IPC分类号： H01L23/62

CPC分类号： H01L27/0266

摘要： A layout structure for an ESD protection circuit includes a first MOS device area having a first and second doped regions of the same polarity disposed at two sides of a first conductive gate layer, and a third doped region disposed along the first doped region at one side of the first conductive gate layer. The third doped region has a polarity different from that of the first and second doped regions, such that the third doped region and the second doped region form a diode for enhancing dissipation of ESD current during a negative ESD event.

摘要翻译： ESD保护电路的布局结构包括：第一MOS器件区域，具有设置在第一导电栅极层的两侧的具有相同极性的第一和第二掺杂区域;以及第三掺杂区域，沿第一掺杂区域设置在一侧 的第一导电栅极层。 第三掺杂区域具有与第一和第二掺杂区域不同的极性，使得第三掺杂区域和第二掺杂区域形成用于在负ESD事件期间增强ESD电流的耗散的二极管。