公开(公告)号：US5877993A

公开(公告)日：1999-03-02

申请号：US855555

申请日：1997-05-13

申请人： Kurt D. Biegel ,  Douglas J. Cutter ,  Manny K. Ma ,  Gordon D. Roberts ,  James E. Miller ,  Daryl L. Habersetzer ,  Jeffrey D. Bruce ,  Eric T. Stubbs

发明人： Kurt D. Biegel ,  Douglas J. Cutter ,  Manny K. Ma ,  Gordon D. Roberts ,  James E. Miller ,  Daryl L. Habersetzer ,  Jeffrey D. Bruce ,  Eric T. Stubbs

IPC分类号： G11C7/00 ,  G11C29/02 ,  G11C29/12 ,  G11C29/44 ,  G11C29/48 ,  G11C29/50 ,  G11C29/56

CPC分类号： G11C29/026 ,  G11C29/02 ,  G11C29/025 ,  G11C29/028 ,  G11C29/12 ,  G11C29/44 ,  G11C29/48 ,  G11C29/50 ,  G11C29/50012 ,  G11C29/56 ,  G11C11/401 ,  G11C2029/5004

摘要： As part of a memory array, a circuit is provided for altering the drive applied to an access transistor that regulates electrical communication within the memory array. In one embodiment, the circuit is used to alter the drive applied to a sense amp's voltage-pulling transistor, thereby allowing modification of the voltage-pulling rate for components of the sense amp. A sample of test data is written to the memory array and read several times at varying drive rates in order to determine the sense amp's ability to accommodate external circuitry. In another embodiment, the circuit is used to alter the drive applied to a bleeder device that regulates communication between the digit lines of the memory array and its cell plate. Slowing said communication allows defects within the memory array to have a more pronounced effect and hence increases the chances of finding such defects during testing. The circuit is configured to accept and apply a plurality of voltages, either through a contact pad or from a series of discrete voltage sources coupled to the circuit.

公开(公告)号：US06452846B1

公开(公告)日：2002-09-17

申请号：US09733434

申请日：2000-12-08

申请人： Kurt D. Beigel ,  Douglas J. Cutter ,  Manny K. Ma ,  Gordon D. Roberts ,  James E. Miller ,  Daryl L. Habersetzer ,  Jeffrey D. Bruce ,  Eric T. Stubbs

发明人： Kurt D. Beigel ,  Douglas J. Cutter ,  Manny K. Ma ,  Gordon D. Roberts ,  James E. Miller ,  Daryl L. Habersetzer ,  Jeffrey D. Bruce ,  Eric T. Stubbs

IPC分类号： G11C700

CPC分类号： G11C29/026 ,  G11C11/401 ,  G11C29/02 ,  G11C29/025 ,  G11C29/028 ,  G11C29/12 ,  G11C29/44 ,  G11C29/48 ,  G11C29/50 ,  G11C29/50012 ,  G11C29/56 ,  G11C2029/5004

摘要： As part of a memory array, a circuit is provided for altering the drive applied to an access transistor that regulates electrical communication within the memory array. In one embodiment, the circuit is used to alter the drive applied to a sense amp's voltage-pulling transistor, thereby allowing modification of the voltage-pulling rate for components of the sense amp. A sample of test data is written to the memory array and read several times at varying drive rates in order to determine the sense amp's ability to accommodate external circuitry. In another embodiment, the circuit is used to alter the drive applied to a bleeder device that regulates communication between the digit lines of the memory array and its cell plate. Slowing said communication allows defects within the memory array to have a more pronounced effect and hence increases the chances of finding such defects during testing. The circuit is configured to accept and apply a plurality of voltages, either through a contact pad or from a series of discrete voltage sources coupled to the circuit.

摘要翻译： 作为存储器阵列的一部分，提供了用于改变施加到调节存储器阵列内的电通信的存取晶体管的驱动电路的电路。 在一个实施例中，该电路用于改变施加到感测放大器的电压 - 牵引晶体管的驱动，从而允许改变感测放大器部件的电压提升率。 将测试数据的样本写入存储器阵列，并以变化的驱动速率读取数次，以便确定感测放大器容纳外部电路的能力。 在另一个实施例中，电路用于改变施加到泄放装置的驱动，其调节存储器阵列的数字线与其单元板之间的通信。 减轻所述通信允许存储器阵列中的缺陷具有更显着的效果，并因此增加在测试期间发现这些缺陷的机会。 电路被配置为通过接触焊盘或耦合到电路的一系列离散电压源来接受和施加多个电压。

公开(公告)号：US6052322A

公开(公告)日：2000-04-18

申请号：US363003

申请日：1999-07-28

申请人： Kurt D. Beigel ,  Douglas J. Cutter ,  Manny K. Ma ,  Gordon D. Roberts ,  James E. Miller ,  Daryl L. Habersetzer ,  Jeffrey D. Bruce ,  Eric T. Stubbs

发明人： Kurt D. Beigel ,  Douglas J. Cutter ,  Manny K. Ma ,  Gordon D. Roberts ,  James E. Miller ,  Daryl L. Habersetzer ,  Jeffrey D. Bruce ,  Eric T. Stubbs

IPC分类号： G11C7/00 ,  G11C29/02 ,  G11C29/12 ,  G11C29/44 ,  G11C29/48 ,  G11C29/50 ,  G11C29/56

CPC分类号： G11C29/026 ,  G11C29/02 ,  G11C29/025 ,  G11C29/028 ,  G11C29/12 ,  G11C29/44 ,  G11C29/48 ,  G11C29/50 ,  G11C29/50012 ,  G11C29/56 ,  G11C11/401 ,  G11C2029/5004

摘要： As part of a memory array, a circuit is provided for altering the drive applied to an access transistor that regulates electrical communication within the memory array. In one embodiment, the circuit is used to alter the drive applied to a sense amp's voltage-pulling transistor, thereby allowing modification of the voltage-pulling rate for components of the sense amp. A sample of test data is written to the memory array and read several times at varying drive rates in order to determine the sense amp's ability to accommodate external circuitry. In another embodiment, the circuit is used to alter the drive applied to a bleeder device that regulates communication between the digit lines of the memory array and its cell plate. Slowing said communication allows defects within the memory array to have a more pronounced effect and hence increases the chances of finding such defects during testing. The circuit is configured to accept and apply a plurality of voltages, either through a contact pad or from a series of discrete voltage sources coupled to the circuit.

摘要翻译： 作为存储器阵列的一部分，提供了用于改变施加到调节存储器阵列内的电通信的存取晶体管的驱动电路的电路。 在一个实施例中，该电路用于改变施加到感测放大器的电压 - 牵引晶体管的驱动，从而允许改变感测放大器部件的电压提升率。 将测试数据的样本写入存储器阵列，并以变化的驱动速率读取数次，以便确定感测放大器容纳外部电路的能力。 在另一个实施例中，电路用于改变施加到泄放装置的驱动，其调节存储器阵列的数字线与其单元板之间的通信。 减轻所述通信允许存储器阵列中的缺陷具有更显着的效果，并因此增加在测试期间发现这些缺陷的机会。 电路被配置为通过接触焊盘或耦合到电路的一系列离散电压源来接受和施加多个电压。

公开(公告)号：US6026040A

公开(公告)日：2000-02-15

申请号：US259220

申请日：1999-03-01

申请人： Kurt D. Beigel ,  Douglas J. Cutter ,  Manny K. Ma ,  Gordon D. Roberts ,  James E. Miller ,  Daryl L. Habersetzer ,  Jeffrey D. Bruce ,  Eric T. Stubbs

发明人： Kurt D. Beigel ,  Douglas J. Cutter ,  Manny K. Ma ,  Gordon D. Roberts ,  James E. Miller ,  Daryl L. Habersetzer ,  Jeffrey D. Bruce ,  Eric T. Stubbs

IPC分类号： G11C7/00 ,  G11C29/02 ,  G11C29/12 ,  G11C29/44 ,  G11C29/48 ,  G11C29/50 ,  G11C29/56

CPC分类号： G11C29/026 ,  G11C29/02 ,  G11C29/025 ,  G11C29/028 ,  G11C29/12 ,  G11C29/44 ,  G11C29/48 ,  G11C29/50 ,  G11C29/50012 ,  G11C29/56 ,  G11C11/401 ,  G11C2029/5004

摘要： As part of a memory array, a circuit is provided for altering the drive applied to an access transistor that regulates electrical communication within the memory array. In one embodiment, the circuit is used to alter the drive applied to a sense amp's voltage-pulling transistor, thereby allowing modification of the voltage-pulling rate for components of the sense amp. A sample of test data is written to the memory array and read several times at varying drive rates in order to determine the sense amp's ability to accommodate external circuitry. In another embodiment, the circuit is used to alter the drive applied to a bleeder device that regulates communication between the digit lines of the memory array and its cell plate. Slowing said communication allows defects within the memory array to have a more pronounced effect and hence increases the chances of finding such defects during testing. The circuit is configured to accept and apply a plurality of voltages, either through a contact pad or from a series of discrete voltage sources coupled to the circuit.

摘要翻译： 作为存储器阵列的一部分，提供了用于改变施加到调节存储器阵列内的电通信的存取晶体管的驱动电路的电路。 在一个实施例中，该电路用于改变施加到感测放大器的电压 - 牵引晶体管的驱动，从而允许改变感测放大器部件的电压提升率。 将测试数据的样本写入存储器阵列，并以变化的驱动速率读取数次，以便确定感测放大器容纳外部电路的能力。 在另一个实施例中，电路用于改变施加到泄放装置的驱动，其调节存储器阵列的数字线与其单元板之间的通信。 减轻所述通信允许存储器阵列中的缺陷具有更显着的效果，并因此增加在测试期间发现这些缺陷的机会。 电路被配置为通过接触焊盘或耦合到电路的一系列离散电压源来接受和施加多个电压。

公开(公告)号：US06335888B2

公开(公告)日：2002-01-01

申请号：US09735120

申请日：2000-12-11

申请人： Kurt D. Beigel ,  Douglas J. Cutter ,  Manny K. Ma ,  Gordon D. Roberts ,  James E. Miller ,  Daryl L. Habersetzer ,  Jeffrey D. Bruce ,  Eric T. Stubbs

发明人： Kurt D. Beigel ,  Douglas J. Cutter ,  Manny K. Ma ,  Gordon D. Roberts ,  James E. Miller ,  Daryl L. Habersetzer ,  Jeffrey D. Bruce ,  Eric T. Stubbs

IPC分类号： G11C700

CPC分类号： G11C29/026 ,  G11C11/401 ,  G11C29/02 ,  G11C29/025 ,  G11C29/028 ,  G11C29/12 ,  G11C29/44 ,  G11C29/48 ,  G11C29/50 ,  G11C29/50012 ,  G11C29/56 ,  G11C2029/5004

摘要： As part of a memory array, a circuit is provided for altering the drive applied to an access transistor that regulates electrical communication within the memory array. In one embodiment, the circuit is used to alter the drive applied to a sense amp's voltage-pulling transistor, thereby allowing modification of the voltage-pulling rate for components of the sense amp. A sample of test data is written to the memory array and read several times at varying drive rates in order to determine the sense amp's ability to accommodate external circuitry. In another embodiment, the circuit is used to alter the drive applied to a bleeder device that regulates communication between the digit lines of the memory array and its cell plate. Slowing said communication allows defects within the memory array to have a more pronounced effect and hence increases the chances of finding such defects during testing. The circuit is configured to accept and apply a plurality of voltages, either through a contact pad or from a series of discrete voltage sources coupled to the circuit.

摘要翻译： 作为存储器阵列的一部分，提供了用于改变施加到调节存储器阵列内的电通信的存取晶体管的驱动电路的电路。 在一个实施例中，该电路用于改变施加到感测放大器的电压 - 牵引晶体管的驱动，从而允许改变感测放大器部件的电压提升率。 将测试数据的样本写入存储器阵列，并以变化的驱动速率读取数次，以便确定感测放大器容纳外部电路的能力。 在另一个实施例中，电路用于改变施加到泄放装置的驱动，其调节存储器阵列的数字线与其单元板之间的通信。 减轻所述通信允许存储器阵列中的缺陷具有更显着的效果，并因此增加在测试期间发现这些缺陷的机会。 电路被配置为通过接触焊盘或耦合到电路的一系列离散电压源来接受和施加多个电压。

公开(公告)号：US06198676B1

公开(公告)日：2001-03-06

申请号：US09483266

申请日：2000-01-11

申请人： Kurt D. Beigel ,  Douglas J. Cutter ,  Manny K. Ma ,  Gordon D. Roberts ,  James E. Miller ,  Daryl L. Habersetzer ,  Jeffrey D. Bruce ,  Eric T. Stubbs

发明人： Kurt D. Beigel ,  Douglas J. Cutter ,  Manny K. Ma ,  Gordon D. Roberts ,  James E. Miller ,  Daryl L. Habersetzer ,  Jeffrey D. Bruce ,  Eric T. Stubbs

IPC分类号： G11C700

CPC分类号： G11C29/026 ,  G11C11/401 ,  G11C29/02 ,  G11C29/025 ,  G11C29/028 ,  G11C29/12 ,  G11C29/44 ,  G11C29/48 ,  G11C29/50 ,  G11C29/50012 ,  G11C29/56 ,  G11C2029/5004

摘要： As part of a memory array, a circuit is provided for altering the drive applied to an access transistor that regulates electrical communication within the memory array. In one embodiment, the circuit is used to alter the drive applied to a sense amp's voltage-pulling transistor, thereby allowing modification of the voltage-pulling rate for components of the sense amp. A sample of test data is written to the memory array and read several times at varying drive rates in order to determine the sense amp's ability to accommodate external circuitry. In another embodiment, the circuit is used to alter the drive applied to a bleeder device that regulates communication between the digit lines of the memory array and its cell plate. Slowing said communication allows defects within the memory array to have a more pronounced effect and hence increases the chances of finding such defects during testing. The circuit is configured to accept and apply a plurality of voltages, either through a contact pad or from a series of discrete voltage sources coupled to the circuit.

摘要翻译： 作为存储器阵列的一部分，提供了用于改变施加到调节存储器阵列内的电通信的存取晶体管的驱动电路的电路。 在一个实施例中，该电路用于改变施加到感测放大器的电压 - 牵引晶体管的驱动，从而允许改变感测放大器部件的电压提升率。 将测试数据的样本写入存储器阵列，并以变化的驱动速率读取数次，以便确定感测放大器容纳外部电路的能力。 在另一个实施例中，电路用于改变施加到泄放装置的驱动，其调节存储器阵列的数字线与其单元板之间的通信。 减轻所述通信允许存储器阵列中的缺陷具有更显着的效果，并因此增加在测试期间发现这些缺陷的机会。 电路被配置为通过接触焊盘或耦合到电路的一系列离散电压源来接受和施加多个电压。

公开(公告)号：US06181617B2

公开(公告)日：2001-01-30

申请号：US09483549

申请日：2000-01-14

申请人： Kurt D. Beigel ,  Douglas J. Cutter ,  Manny K. Ma ,  Gordon D. Roberts ,  James E. Miller ,  Daryl L. Habersetzer ,  Jeffrey D Bruce ,  Eric T. Stubbs

发明人： Kurt D. Beigel ,  Douglas J. Cutter ,  Manny K. Ma ,  Gordon D. Roberts ,  James E. Miller ,  Daryl L. Habersetzer ,  Jeffrey D Bruce ,  Eric T. Stubbs

IPC分类号： G11C700

CPC分类号： G11C29/026 ,  G11C11/401 ,  G11C29/02 ,  G11C29/025 ,  G11C29/028 ,  G11C29/12 ,  G11C29/44 ,  G11C29/48 ,  G11C29/50 ,  G11C29/50012 ,  G11C29/56 ,  G11C2029/5004

摘要： As part of a memory array, a circuit is provided for altering the drive applied to an access transistor that regulates electrical communication within the memory array. In one embodiment, the circuit is used to alter the drive applied to a sense amp's voltage-pulling transistor, thereby allowing modification of the voltage-pulling rate for components of the sense amp. A sample of test data is written to the memory array and read several times at varying drive rates in order to determine the sense amp's ability to accommodate external circuitry. In another embodiment, the circuit is used to alter the drive applied to a bleeder device that regulates communication between the digit lines of the memory array and its cell plate. Slowing said communication allows defects within the memory array to have a more pronounced effect and hence increases the chances of finding such defects during testing. The circuit is configured to accept and apply a plurality of voltages, either through a contact pad or from a series of discrete voltage sources coupled to the circuit.

摘要翻译： 作为存储器阵列的一部分，提供了用于改变施加到调节存储器阵列内的电通信的存取晶体管的驱动电路的电路。 在一个实施例中，该电路用于改变施加到感测放大器的电压 - 牵引晶体管的驱动，从而允许改变感测放大器部件的电压提升率。 将测试数据的样本写入存储器阵列，并以变化的驱动速率读取数次，以便确定感测放大器容纳外部电路的能力。 在另一个实施例中，电路用于改变施加到泄放装置的驱动，其调节存储器阵列的数字线与其单元板之间的通信。 减轻所述通信允许存储器阵列中的缺陷具有更显着的效果，并因此增加在测试期间发现这些缺陷的机会。 电路被配置为通过接触焊盘或耦合到电路的一系列离散电压源来接受和施加多个电压。

公开(公告)号：US06778452B2

公开(公告)日：2004-08-17

申请号：US10608060

申请日：2003-06-27

申请人： Kurt D. Beigel ,  Douglas J. Cutter ,  Manny K. Ma ,  Gordon D. Roberts ,  James E. Miller ,  Daryl L. Habersetzer ,  Jeffrey D. Bruce ,  Eric T. Stubbs

发明人： Kurt D. Beigel ,  Douglas J. Cutter ,  Manny K. Ma ,  Gordon D. Roberts ,  James E. Miller ,  Daryl L. Habersetzer ,  Jeffrey D. Bruce ,  Eric T. Stubbs

IPC分类号： G11C700

CPC分类号： G11C29/026 ,  G11C11/401 ,  G11C29/02 ,  G11C29/025 ,  G11C29/028 ,  G11C29/12 ,  G11C29/44 ,  G11C29/48 ,  G11C29/50 ,  G11C29/50012 ,  G11C29/56 ,  G11C2029/5004

摘要： As part of a memory array, a circuit is provided for altering the drive applied to an access transistor that regulates electrical communication within the memory array. In one embodiment, the circuit is used to alter the drive applied to a sense amp's voltage-pulling transistor, thereby allowing modification of the voltage-pulling rate for components of the sense amp. A sample of test data is written to the memory array and read several times at varying drive rates in order to determine the sense amp's ability to accommodate external circuitry. In another embodiment, the circuit is used to alter the drive applied to a bleeder device that regulates communication between the digit lines of the memory array and its cell plate. Slowing said communication allows defects within the memory array to have a more pronounced effect and hence increases the chances of finding such defects during testing. The circuit is configured to accept and apply a plurality of voltages, either through a contact pad or from a series of discrete voltage sources coupled to the circuit.

公开(公告)号：US06445629B1

公开(公告)日：2002-09-03

申请号：US09735330

申请日：2000-12-11

申请人： Kurt D. Beigel ,  Douglas J. Cutter ,  Manny K. Ma ,  Gordon D. Roberts ,  James E. Miller ,  Daryl L. Habersetzer ,  Jeffrey D. Bruce ,  Eric T. Stubbs

发明人： Kurt D. Beigel ,  Douglas J. Cutter ,  Manny K. Ma ,  Gordon D. Roberts ,  James E. Miller ,  Daryl L. Habersetzer ,  Jeffrey D. Bruce ,  Eric T. Stubbs

IPC分类号： G11C700

摘要： As part of a memory array, a circuit is provided for altering the drive applied to an access transistor that regulates electrical communication within the memory array. In one embodiment, the circuit is used to alter the drive applied to a sense amp's voltage-pulling transistor, thereby allowing modification of the voltage-pulling rate for components of the sense amp. A sample of test data is written to the memory array and read several times at varying drive rates in order to determine the sense amp's ability to accommodate external circuitry. In another embodiment, the circuit is used to alter the drive applied to a bleeder device that regulates communication between the digit lines of the memory array and its cell plate. Slowing said communication allows defects within the memory array to have a more pronounced effect and hence increases the chances of finding such defects during testing. The circuit is configured to accept and apply a plurality of voltages, either through a contact pad or from a series of discrete voltage sources coupled to the circuit.

公开(公告)号：US6011731A

公开(公告)日：2000-01-04

申请号：US259221

申请日：1999-03-01

申请人： Kurt D. Beigel ,  Manny K. Ma ,  Gordon D. Roberts ,  James E. Miller ,  Daryl L. Habersetzer ,  Jeffrey D. Bruce ,  Eric T. Stubbs

发明人： Kurt D. Beigel ,  Manny K. Ma ,  Gordon D. Roberts ,  James E. Miller ,  Daryl L. Habersetzer ,  Jeffrey D. Bruce ,  Eric T. Stubbs

IPC分类号： G11C7/00 ,  G11C29/02 ,  G11C29/12 ,  G11C29/44 ,  G11C29/48 ,  G11C29/50 ,  G11C29/56

CPC分类号： G11C29/026 ,  G11C29/02 ,  G11C29/025 ,  G11C29/028 ,  G11C29/12 ,  G11C29/44 ,  G11C29/48 ,  G11C29/50 ,  G11C29/50012 ,  G11C29/56 ,  G11C11/401 ,  G11C2029/5004

摘要： As part of a memory array, a circuit is provided for altering the drive applied to an access transistor that regulates electrical communication within the memory array. In one embodiment, the circuit is used to alter the drive applied to a sense amp's voltage-pulling transistor, thereby allowing modification of the voltage-pulling rate for components of the sense amp. A sample of test data is written to the memory array and read several times at varying drive rates in order to determine the sense amp's ability to accommodate external circuitry. In another embodiment, the circuit is used to alter the drive applied to a bleeder device that regulates communication between the digit lines of the memory array and its cell plate. Slowing said communication allows defects within the memory array to have a more pronounced effect and hence increases the chances of finding such defects during testing. The circuit is configured to accept and apply a plurality of voltages, either through a contact pad or from a series of discrete voltage sources coupled to the circuit.

摘要翻译： 作为存储器阵列的一部分，提供了用于改变施加到调节存储器阵列内的电通信的存取晶体管的驱动电路的电路。 在一个实施例中，该电路用于改变施加到感测放大器的电压 - 牵引晶体管的驱动，从而允许改变感测放大器部件的电压提升率。 将测试数据的样本写入存储器阵列，并以变化的驱动速率读取数次，以便确定感测放大器容纳外部电路的能力。 在另一个实施例中，电路用于改变施加到泄放装置的驱动，其调节存储器阵列的数字线与其单元板之间的通信。 减轻所述通信允许存储器阵列中的缺陷具有更显着的效果，并因此增加在测试期间发现这些缺陷的机会。 电路被配置为通过接触焊盘或耦合到电路的一系列离散电压源来接受和施加多个电压。