公开(公告)号：US09136717B2

公开(公告)日：2015-09-15

申请号：US13040891

申请日：2011-03-04

申请人： Kyouichi Kashima ,  Yoshitaka Fukushima ,  Masahiro Ono ,  Tetsuro Hirano

发明人： Kyouichi Kashima ,  Yoshitaka Fukushima ,  Masahiro Ono ,  Tetsuro Hirano

IPC分类号： H02H3/00 ,  H02H7/00 ,  H02J7/00 ,  H02H9/00 ,  H02H3/20 ,  H02H9/04 ,  H02H3/22

CPC分类号： H02J7/0016

摘要： A circuit device connected between a neighboring pair of terminals in a semiconductor integrated circuit is protected from electrostatic damage due to a surge voltage when the surge voltage is applied between the neighboring pair of terminals. The semiconductor integrated circuit is formed to include terminals P0-P14, MOS transistors MN0-MN15 in diode connection, protection diode circuits HD0-HD14, MOS transistors T1-T14 for discharging electricity from batteries, a battery voltage detection control circuit and a clamp circuit for overvoltage protection. Each of the MOS transistors T1-T14 for discharging electricity from the batteries is connected between each neighboring pair of the terminals P0-P14 through wirings. Each of the MOS transistors MN1-MN14 in diode connection is connected between each neighboring pair of the terminals.

摘要翻译： 当在相邻的一对端子之间施加浪涌电压时，连接在半导体集成电路中的相邻的一对端子之间的电路装置被防止由于浪涌电压的静电损伤。 半导体集成电路形成为包括端子P0-P14，二极管连接的MOS晶体管MN0-MN15，保护二极管电路HD0-HD14，用于从电池放电的MOS晶体管T1-T14，电池电压检测控制电路和钳位电路 用于过电压保护。 用于从电池放电的MOS晶体管T1-T14中的每一个通过布线连接在每个相邻的一对端子P0-P14之间。 二极管连接的MOS晶体管MN1〜MN14中的每一个连接在每个相邻的一对端子之间。

公开(公告)号：US20110235224A1

公开(公告)日：2011-09-29

申请号：US13040891

申请日：2011-03-04

申请人： Kyouichi KASHIMA ,  Yoshitaka Fukushima ,  Masahiro Ono ,  Tetsuro Hirano

发明人： Kyouichi KASHIMA ,  Yoshitaka Fukushima ,  Masahiro Ono ,  Tetsuro Hirano

IPC分类号： H02H3/00

CPC分类号： H02J7/0016

摘要： A circuit device connected between a neighboring pair of terminals in a semiconductor integrated circuit is protected from electrostatic damage due to a surge voltage when the surge voltage is applied between the neighboring pair of terminals. The semiconductor integrated circuit is formed to include terminals P0-P14, MOS transistors MN0-MN15 in diode connection, protection diode circuits HD0-HD14, MOS transistors T1-T14 for discharging electricity from batteries, a battery voltage detection control circuit and a clamp circuit for overvoltage protection. Each of the MOS transistors T1-T14 for discharging electricity from the batteries is connected between each neighboring pair of the terminals P0-P14 through wirings. Each of the MOS transistors MN1-MN14 in diode connection is connected between each neighboring pair of the terminals.

摘要翻译： 当在相邻的一对端子之间施加浪涌电压时，连接在半导体集成电路中的相邻的一对端子之间的电路装置被防止由于浪涌电压引起的静电损伤。 半导体集成电路形成为包括端子P0-P14，二极管连接的MOS晶体管MN0-MN15，保护二极管电路HD0-HD14，用于从电池放电的MOS晶体管T1-T14，电池电压检测控制电路和钳位电路 用于过电压保护。 用于从电池放电的MOS晶体管T1-T14中的每一个通过布线连接在每个相邻的一对端子P0-P14之间。 二极管连接的MOS晶体管MN1〜MN14中的每一个连接在每个相邻的一对端子之间。

公开(公告)号：US08723258B2

公开(公告)日：2014-05-13

申请号：US13229201

申请日：2011-09-09

申请人： Kiyofumi Nakaya ,  Tetsuro Hirano ,  Shuji Fujiwara

发明人： Kiyofumi Nakaya ,  Tetsuro Hirano ,  Shuji Fujiwara

IPC分类号： H01L29/66 ,  H01L29/06 ,  H01L29/78 ,  H01L29/08

CPC分类号： H01L29/0696 ,  H01L27/027 ,  H01L29/0856 ,  H01L29/1095 ,  H01L29/7816

摘要： An ESD tolerance of an LDMOS transistor is improved. An N+ type source layer shaped in a ladder and having a plurality of openings in its center is formed in a surface of a P type base layer using a gate electrode and a resist mask. A P+ type contact layer is formed to be buried in the opening. At that time, a distance from an edge of the opening, that is an edge of the P+ type contact layer, to an edge of the N+ type source layer is set to a predetermined distance. The predetermined distance is equal to a distance at which an HBM+ESD tolerance of the LDMOS transistor, which increases as the distance increases, begins to saturate.

摘要翻译： 提高了LDMOS晶体管的ESD耐受性。 使用栅极和抗蚀剂掩模在P型基底层的表面上形成梯形并且在其中心具有多个开口的N +型源极层。 形成P +型接触层以埋入开口中。 此时，从开口的边缘（即P +型接触层的边缘）到N +型源极层的边缘的距离被设定为预定距离。 预定距离等于距离增加时增加的LDMOS晶体管的HBM + ESD容限的距离开始饱和。