专利检索 ap:("Kyung-Youl Min" OR "Yong-Sik Seok") AND inv:"Kyung-Youl Min" 第 1 页

1.

发明授权
Circuit for generating a clock signal to separate bit lines in a semiconductor memory device 失效
标题翻译：用于产生时钟信号以在半导体存储器件中分离位线的电路

公开(公告)号：US5402378A

公开(公告)日：1995-03-28

申请号：US972522

申请日：1992-11-06

申请人： Kyung-Youl Min , Yong-Sik Seok

发明人： Kyung-Youl Min , Yong-Sik Seok

IPC分类号： G11C11/417 , G11C5/14 , G11C7/12 , G11C7/18 , G11C7/22 , G11C11/401 , G11C11/407 , G11C11/409 , G11C7/00

CPC分类号： G11C7/12 , G11C5/14 , G11C7/18 , G11C7/22

摘要： A semiconductor memory device using a low level supply voltage has separation gates for isolating adjacent bit lines. The device may be constructed with a circuit for receiving a high voltage supplied by a high voltage generator resident upon the chip so as to provide the separation gates with a voltage increased at least by the amount of the threshold voltage of the separation gates over the supply voltage.

摘要翻译： 使用低电平电源电压的半导体存储器件具有用于隔离相邻位线的分离栅极。该器件可以构造有用于接收由驻留在芯片上的高电压发生器提供的高电压的电路，以便为分离门提供至少增加电源上的分离门的阈值电压的量的电压电压。