公开(公告)号：US20140132875A1

公开(公告)日：2014-05-15

申请号：US14059138

申请日：2013-10-21

Applicant: LG DISPLAY CO., LTD.

Inventor： Yeong-Hyeok Yun ,  Hyuck Choi ,  Won-Doo Kim

IPC: G02F1/1343 ,  H01L29/66

CPC classification number: H01L29/66742 ,  G02F1/136227 ,  G02F1/136286 ,  G02F2001/136231 ,  H01L27/124

Abstract: An array substrate for a liquid crystal display (LCD) device includes a common line and gate lines. The array substrate includes a first, second, and third passivation layer and thin film transistors (TFTs). The second passivation layer includes first and second holes respectively corresponding to a drain electrode and the common line. A common electrode on the second passivation layer includes a first opening corresponding to the TFTs and a second opening in the second hole. A drain contact hole through the third and first passivation layers exposes the drain electrode. A first common contact hole through the third passivation layer exposes the common electrode in the second hole. A second common contact hole through the third and first passivation layers exposes the common line, and a pixel electrode includes a third opening and a connection pattern connecting the common electrode to the common line on the third passivation layer.

Abstract translation: 用于液晶显示（LCD）装置的阵列基板包括公共线和栅极线。 阵列基板包括第一，第二和第三钝化层和薄膜晶体管（TFT）。 第二钝化层包括分别对应于漏电极和公共线的第一和第二孔。 第二钝化层上的公共电极包括对应于TFT的第一开口和第二孔中的第二开口。 穿过第三钝化层和第一钝化层的漏极接触孔露出漏电极。 通过第三钝化层的第一公共接触孔暴露第二孔中的公共电极。 通过第三和第一钝化层的第二公共接触孔露出公共线，并且像素电极包括第三开口和将公共电极连接到第三钝化层上的公共线的连接图案。

公开(公告)号：US09768275B2

公开(公告)日：2017-09-19

申请号：US14059138

申请日：2013-10-21

Applicant: LG DISPLAY CO., LTD.

Inventor： Yeong-Hyeok Yun ,  Hyuck Choi ,  Won-Doo Kim

IPC: G02F1/1343 ,  H01L29/66 ,  G02F1/1362 ,  H01L27/12

CPC classification number: H01L29/66742 ,  G02F1/136227 ,  G02F1/136286 ,  G02F2001/136231 ,  H01L27/124

Abstract: An array substrate for a liquid crystal display (LCD) device includes a common line and gate lines. The array substrate includes a first, second, and third passivation layer and thin film transistors (TFTs). The second passivation layer includes first and second holes respectively corresponding to a drain electrode and the common line. A common electrode on the second passivation layer includes a first opening corresponding to the TFTs and a second opening in the second hole. A drain contact hole through the third and first passivation layers exposes the drain electrode. A first common contact hole through the third passivation layer exposes the common electrode in the second hole. A second common contact hole through the third and first passivation layers exposes the common line, and a pixel electrode includes a third opening and a connection pattern connecting the common electrode to the common line on the third passivation layer.