公开(公告)号：US11315497B2

公开(公告)日：2022-04-26

申请号：US16943579

申请日：2020-07-30

Applicant: LG Display Co., Ltd.

Inventor： Jaesung Yu ,  Chungsik Kong ,  Sewan Lee ,  Juhnsuk Yoo ,  Jungsoo Park ,  Mihee Shin

IPC: G09G3/3266 ,  G09G3/20 ,  G09G3/3225 ,  G09G3/3275 ,  G09G3/36

Abstract: A gate driving circuit and an image display device including the gate driving circuit are provided. In some embodiments of the present disclosure, the gate driving circuit includes a plurality of stages configured to sequentially and repeatedly output a plurality of scan pulses having different pulse widths in response to a gate control signal applied from a timing controller and the plurality of stages sequentially generate the plurality of scan pulses having different pulse widths and phase-delayed in response to three-phase clock pulses among the gate control signals and sequentially supply the plurality of scan pulses to gate lines of a display panel to selectively adjust a light emission period or a color display period for each red pixel, green pixel, and blue pixel, thereby improving image quality.

公开(公告)号：US10762853B2

公开(公告)日：2020-09-01

申请号：US16050129

申请日：2018-07-31

Applicant: LG Display Co., Ltd.

Inventor： Chungsik Kong ,  Honggyu Han ,  Mihee Shin ,  Sewan Lee

IPC: G11C19/00 ,  G09G3/3291 ,  G11C19/28 ,  G09G3/3266 ,  G09G3/36

Abstract: An organic light emitting display comprises pixels connected to gate lines, and a gate driving circuit to supply a gate signal to at least one gate line, and having stages connected to each other in a cascading way. A nth (n is a positive integer) stage of the gate driving circuit includes a Q1 node charging unit to charge a Q1 node to a turn-on voltage using first and second clock signals in reverse-phase, and a pull-up transistor to apply the turn-on voltage to an output terminal in response to a Q1 node voltage. The Q1 node charging unit includes a first charging unit to charge the Q1 node voltage to the turn-on voltage using the second clock signal; and a second charging unit to charge a Q2 node, coupled to the Q1 node, using the first clock signal in a section where the Q1 node has the turn-on voltage.

公开(公告)号：US09824771B2

公开(公告)日：2017-11-21

申请号：US14133243

申请日：2013-12-18

Applicant: LG DISPLAY CO., LTD.

Inventor： Sunghyun Cho ,  Chungsik Kong ,  Sungwook Chang

IPC: G11C19/00 ,  G11C19/28

CPC classification number: G11C19/28 ,  G09G2310/0286

Abstract: Provided is a gate shift register including a plurality of stages receiving a plurality of clocks to generate gate output signals, in which an n-th stage of the stages dependently connected to each other includes an output node outputting an n-th gate output signal, a pull-up TFT switching a current flow between an input terminal of a clock having an n-th phase and the output node according to a potential of a Q node, a pull-down TFT switching the current flow between an input terminal of a low potential voltage and the output node according to a potential of a QB node, appnd a BTS compensation unit periodically discharging the QB node at a low potential level just after the n-th stage is reset and just until the n-th stage is set in a next frame.