公开(公告)号：US08754410B2

公开(公告)日：2014-06-17

申请号：US13706730

申请日：2012-12-06

Applicant: LG Display Co., Ltd.

Inventor： Heon-Kwang Park ,  Dong-Hun Lim

IPC: H01L29/786 ,  H01L21/336

CPC classification number: H01L29/78693 ,  H01L27/088 ,  H01L29/247 ,  H01L29/41733 ,  H01L29/7869 ,  H01L29/78696

Abstract: An array substrate includes a gate line on a substrate including a pixel region, the gate line extending in one direction; a gate electrode in the pixel region and extending from the gate line; a gate insulating layer on the gate line and the gate electrode; a data line on the gate insulating layer and crossing the gate line to define the pixel region; an oxide semiconductor layer on the gate insulating layer and having three ends, the oxide semiconductor layer corresponding to the gate electrode; an etch stopper on the oxide semiconductor layer to expose the three ends of the oxide semiconductor layer; a source electrode contacting two ends of the three ends of the oxide semiconductor layer and extending from the data line; and a drain electrode contacting one end of the three ends of the oxide semiconductor layer and spaced apart from the source electrode.

Abstract translation: 阵列基板包括在包括像素区域的基板上的栅极线，所述栅极线在一个方向上延伸; 像素区域中的栅电极并从栅极线延伸; 栅极线上的栅极绝缘层和栅电极; 栅极绝缘层上的数据线并与栅极线交叉以限定像素区域; 栅极绝缘层上的氧化物半导体层，具有与端电极相对应的三端的氧化物半导体层; 氧化物半导体层上的蚀刻停止层，以露出氧化物半导体层的三个端部; 源电极接触氧化物半导体层的三端的两端并从数据线延伸; 以及漏极，其与氧化物半导体层的三个端部的一端接触并且与源电极间隔开。