公开(公告)号：US11069301B2

公开(公告)日：2021-07-20

申请号：US16225753

申请日：2018-12-19

Applicant: LG Display Co., Ltd.

Inventor： Soon-Dong Cho ,  Jung-Jae Kim ,  Sang-Uk Lee ,  Hyung-Jin Choe

IPC: G09G3/3275 ,  G09G3/36 ,  G09G3/20

Abstract: A display device can include a gate driver configured to drive gate lines of a panel; a data driver configured to drive data lines of the panel; a timing controller configured to control operations of the gate driver and the data driver; and a level shifter integrated circuit (IC) configured to receive a plurality of control signals from the timing controller, and generate and output a plurality gate control signals for controlling driving of the gate driver, in which the plurality of control signals include an on clock and an off clock, and the level shifter IC stores the on clock and the off clock in buffers based on one or more control signals from the timing controller, generates a plurality of scan clocks by logically processing the on clock and the off clock, and outputs the plurality of scan clocks to the gate driver.

公开(公告)号：US10726766B2

公开(公告)日：2020-07-28

申请号：US16198131

申请日：2018-11-21

Applicant: LG Display Co., Ltd.

Inventor： Soon-Dong Cho ,  Jung-Jae Kim ,  Jae-Won Han ,  Hyung-Jin Choe

IPC: G09G3/20 ,  G09G3/3266 ,  G09G3/3275 ,  G09G3/36

Abstract: Disclosed herein are a display device capable of reducing the number of transmission lines by enabling a master circuit to perform communication with a plurality of slave circuits, which utilize different interfaces, through a common transmission line in a time divisional manner, and an interface method thereof. A timing controller uses a common transmission line of a gamma voltage generator and a level shifter which respectively utilize first and second interfaces and perform communication using the first and second interfaces in a time divisional manner.

公开(公告)号：US20190164470A1

公开(公告)日：2019-05-30

申请号：US16198131

申请日：2018-11-21

Applicant: LG Display Co., Ltd.

Inventor： Soon-Dong Cho ,  Jung-Jae Kim ,  Jae-Won Han ,  Hyung-Jin Choe

IPC: G09G3/20 ,  G09G3/3266

CPC classification number: G09G3/2096 ,  G09G3/2092 ,  G09G3/3266 ,  G09G3/3275 ,  G09G3/3696 ,  G09G2310/08 ,  G09G2320/0233 ,  G09G2320/0673 ,  G09G2330/028 ,  G09G2370/08

Abstract: Disclosed herein are a display device capable of reducing the number of transmission lines by enabling a master circuit to perform communication with a plurality of slave circuits, which utilize different interfaces, through a common transmission line in a time divisional manner, and an interface method thereof. A timing controller uses a common transmission line of a gamma voltage generator and a level shifter which respectively utilize first and second interfaces and perform communication using the first and second interfaces in a time divisional manner.