公开(公告)号：US20200006216A1

公开(公告)日：2020-01-02

申请号：US16453552

申请日：2019-06-26

Applicant: LG DISPLAY CO., LTD.

Inventor： Jungjae KIM ,  Heejung HONG ,  Soondong CHO ,  Hyungjin CHOE

IPC: H01L23/50 ,  H05K1/14 ,  H05K1/18

Abstract: The present disclosure provides an integrated circuit comprising a main body and pins. The main body has a top and a bottom. The pins comprise upper pins placed on the top of the main body, and lower pins placed on the bottom of the main body.

公开(公告)号：US20200020280A1

公开(公告)日：2020-01-16

申请号：US16503050

申请日：2019-07-03

Applicant: LG Display Co., Ltd.

Inventor： Jaewon HAN ,  Soondong CHO ,  Jungjae KIM ,  Sanguk LEE ,  Hyungjin CHOE

IPC: G09G3/3266 ,  G09G3/3291

Abstract: The present disclosure provides a gate clock generator including a counter, a buffer control signal generator, and an output unit. The counter receives control data having rising timing information and falling timing information and a main clock. The counter generates a first output when a value is obtained by counting the main clock from a preset reference time point reaches rising data. The counter further generates a second output when a value is obtained by counting the main clock from the reference time point reaches falling data. The buffer control signal generator generates a first buffer control signal of a gate ON voltage from a timing of the first output to a timing of the second output. The output unit outputs a gate ON voltage of a gate clock during an output period of the gate ON voltage of the first buffer control signal.