公开(公告)号：US20160189613A1

公开(公告)日：2016-06-30

申请号：US14977097

申请日：2015-12-21

Applicant: LG DISPLAY CO., LTD.

Inventor： Jungjae KIM ,  Jaewon HAN

IPC: G09G3/32

CPC classification number: G09G3/3233 ,  G09G3/3291 ,  G09G3/3696 ,  G09G2300/0809 ,  G09G2310/08 ,  G09G2320/0247 ,  G09G2330/028

Abstract: A display device according to an embodiment includes a display panel, a driver, a power supply unit, and a power control unit. The power control unit may control the power supply unit in synchronization with a driving period of a device driving the display panel, and control one or more of synchronization signals of a scan driver, a data driver, and a timing controller and a switching frequency of a power generation transistor of the power supply unit to be synchronized.

Abstract translation: 根据实施例的显示装置包括显示面板，驱动器，电源单元和电源控制单元。 功率控制单元可以与驱动显示面板的设备的驱动周期同步地控制电源单元，并且控制扫描驱动器，数据驱动器和定时控制器的同步信号中的一个或多个以及开关频率 电源单元的发电晶体管被同步。

公开(公告)号：US20200020280A1

公开(公告)日：2020-01-16

申请号：US16503050

申请日：2019-07-03

Applicant: LG Display Co., Ltd.

Inventor： Jaewon HAN ,  Soondong CHO ,  Jungjae KIM ,  Sanguk LEE ,  Hyungjin CHOE

IPC: G09G3/3266 ,  G09G3/3291

Abstract: The present disclosure provides a gate clock generator including a counter, a buffer control signal generator, and an output unit. The counter receives control data having rising timing information and falling timing information and a main clock. The counter generates a first output when a value is obtained by counting the main clock from a preset reference time point reaches rising data. The counter further generates a second output when a value is obtained by counting the main clock from the reference time point reaches falling data. The buffer control signal generator generates a first buffer control signal of a gate ON voltage from a timing of the first output to a timing of the second output. The output unit outputs a gate ON voltage of a gate clock during an output period of the gate ON voltage of the first buffer control signal.