公开(公告)号：US11114372B2

公开(公告)日：2021-09-07

申请号：US16453552

申请日：2019-06-26

Applicant: LG DISPLAY CO., LTD.

Inventor： Jungjae Kim ,  Heejung Hong ,  Soondong Cho ,  Hyungjin Choe

IPC: H01L23/50 ,  H05K1/14 ,  H05K1/18 ,  H01L27/06

Abstract: An integrated circuit includes a main body having a top and a bottom; and upper pins placed on the top of the main body, and lower pins placed on the bottom of the main body, in which each of the upper pins has a first protruding portion protruding toward outside from a side or the top of the main body, and each of the lower pins has a second protruding portion protruding toward outside from the side or the bottom of the main body.

公开(公告)号：US10810946B2

公开(公告)日：2020-10-20

申请号：US16503050

申请日：2019-07-03

Applicant: LG Display Co., Ltd.

Inventor： Jaewon Han ,  Soondong Cho ,  Jungjae Kim ,  Sanguk Lee ,  Hyungjin Choe

IPC: G09G3/3266 ,  G09G3/3291

Abstract: The present disclosure provides a gate clock generator including a counter, a buffer control signal generator, and an output unit. The counter receives control data having rising timing information and falling timing information and a main clock. The counter generates a first output when a value is obtained by counting the main clock from a preset reference time point reaches rising data. The counter further generates a second output when a value is obtained by counting the main clock from the reference time point reaches falling data. The buffer control signal generator generates a first buffer control signal of a gate ON voltage from a timing of the first output to a timing of the second output. The output unit outputs a gate ON voltage of a gate clock during an output period of the gate ON voltage of the first buffer control signal.