公开(公告)号：US11114372B2

公开(公告)日：2021-09-07

申请号：US16453552

申请日：2019-06-26

Applicant: LG DISPLAY CO., LTD.

Inventor： Jungjae Kim ,  Heejung Hong ,  Soondong Cho ,  Hyungjin Choe

IPC: H01L23/50 ,  H05K1/14 ,  H05K1/18 ,  H01L27/06

Abstract: An integrated circuit includes a main body having a top and a bottom; and upper pins placed on the top of the main body, and lower pins placed on the bottom of the main body, in which each of the upper pins has a first protruding portion protruding toward outside from a side or the top of the main body, and each of the lower pins has a second protruding portion protruding toward outside from the side or the bottom of the main body.

公开(公告)号：US10008157B2

公开(公告)日：2018-06-26

申请号：US14973043

申请日：2015-12-17

Applicant: LG DISPLAY CO., LTD.

Inventor： Jungjae Kim ,  Jaewon Han

IPC: G09G3/30 ,  G09G3/3291 ,  G09G3/3225 ,  G09G3/3266

CPC classification number: G09G3/3291 ,  G09G3/3225 ,  G09G3/3266 ,  G09G2310/0278 ,  G09G2320/0209 ,  G09G2320/0223 ,  G09G2320/0233 ,  G09G2330/025 ,  G09G2330/028 ,  G09G2360/16

Abstract: Provided is a display device that includes, for example, a display panel, a driver, a power supply unit, and a timing controller. The power supply unit may supply a voltage to the driver. The power supply unit may perform a compensation operation to vary an output voltage output from the power supply unit itself to correspond to a variation of a load before the load varies.

公开(公告)号：US10810946B2

公开(公告)日：2020-10-20

申请号：US16503050

申请日：2019-07-03

Applicant: LG Display Co., Ltd.

Inventor： Jaewon Han ,  Soondong Cho ,  Jungjae Kim ,  Sanguk Lee ,  Hyungjin Choe

IPC: G09G3/3266 ,  G09G3/3291

Abstract: The present disclosure provides a gate clock generator including a counter, a buffer control signal generator, and an output unit. The counter receives control data having rising timing information and falling timing information and a main clock. The counter generates a first output when a value is obtained by counting the main clock from a preset reference time point reaches rising data. The counter further generates a second output when a value is obtained by counting the main clock from the reference time point reaches falling data. The buffer control signal generator generates a first buffer control signal of a gate ON voltage from a timing of the first output to a timing of the second output. The output unit outputs a gate ON voltage of a gate clock during an output period of the gate ON voltage of the first buffer control signal.

公开(公告)号：US09984619B2

公开(公告)日：2018-05-29

申请号：US14977097

申请日：2015-12-21

Applicant: LG DISPLAY CO., LTD.

Inventor： Jungjae Kim ,  Jaewon Han

IPC: G09G3/32 ,  G09G3/3233 ,  G09G3/3291 ,  G09G3/36

CPC classification number: G09G3/3233 ,  G09G3/3291 ,  G09G3/3696 ,  G09G2300/0809 ,  G09G2310/08 ,  G09G2320/0247 ,  G09G2330/028

Abstract: A display device according to an embodiment includes a display panel, a driver, a power supply unit, and a power control unit. The power control unit may control the power supply unit in synchronization with a driving period of a device driving the display panel, and control one or more of synchronization signals of a scan driver, a data driver, and a timing controller and a switching frequency of a power generation transistor of the power supply unit to be synchronized.

公开(公告)号：US10916189B2

公开(公告)日：2021-02-09

申请号：US16544032

申请日：2019-08-19

Applicant: LG Display Co., Ltd.

Inventor： Soondong Cho ,  Hoon Jang ,  Jongwoo Kim ,  Juno Hur ,  Jungjae Kim ,  Dongju Kim

IPC: G09G3/3225 ,  G09G3/3266 ,  G09G3/3275 ,  G09G3/36

Abstract: A scan driver comprises a level shifter configured to output varied clock signals that have different frequencies for at least two consecutive periods; and a shift register operating based on the varied clock signals output from the level shifter and outputting scan signals.