公开(公告)号：US20170193950A1

公开(公告)日：2017-07-06

申请号：US15378928

申请日：2016-12-14

Applicant: LG Display Co., Ltd.

Inventor： Byunghoon KIM ,  Yongho KIM ,  Kwangsoo KIM ,  Seungchul LEE

IPC: G09G3/36

CPC classification number: G09G3/3677 ,  G09G3/3688 ,  G09G3/3696 ,  G09G2300/0809 ,  G09G2310/0286 ,  G09G2310/0291 ,  G09G2310/08 ,  G09G2320/045

Abstract: In a gate driver, a Q node is shared by two channels to output a scan signal at high level, and a QB node is shared by four channels to output a scan signal at low level. Accordingly, the number of thin-film transistors required to configure four channels of a gate-in-panel (GIP) is reduced, such that the bezel size can be reduced. Further, the gate driver includes a compensation capacitor or a discharge transistor disposed in some of the channels sharing the Q node, such that deviation in output characteristics among the channels sharing the Q node can be reduced.

公开(公告)号：US20240185799A1

公开(公告)日：2024-06-06

申请号：US18508340

申请日：2023-11-14

Applicant: LG Display Co., Ltd.

Inventor： Jaesung PARK ,  Kwangsoo KIM

IPC: G09G3/3266

CPC classification number: G09G3/3266 ,  G09G2300/0408 ,  G09G2310/0291

Abstract: Disclosed herein are a gate driving circuit having a small-area structure and a display device, and more specifically, each of a plurality of stage circuits included in the gate driving circuit includes a sensing part, a logic part, and a buffer group, first to fourth scan clock signals and a first carry clock signal are electrically connected to a first stage circuit, and fifth to eighth scan clock signals and a second carry clock signal are electrically connected to a second stage circuit.

公开(公告)号：US20220208112A1

公开(公告)日：2022-06-30

申请号：US17557122

申请日：2021-12-21

Applicant: LG DISPLAY CO., LTD.

Inventor： Kwangsoo KIM ,  Yongho KIM ,  Minkyu CHANG

IPC: G09G3/3266

Abstract: A gate driver circuit includes a plurality of stage circuits, each stage circuit supplies a gate signal to each of gate lines arranged in a display panel and includes a M node, a Q node, a QH node, and a QB node, and each stage circuit includes a line selector, a Q node controller, a Q node and QH node stabilizer, an inverter, a QB node stabilizer, a carry signal output module, and a gate signal output module, and a high voltage level period of a carry clock signal is set not to overlap with a high voltage level period of a first scan clock signal.