Display Apparatus and Driving Method Thereof

    公开(公告)号:US20240203333A1

    公开(公告)日:2024-06-20

    申请号:US18514342

    申请日:2023-11-20

    Abstract: A display apparatus includes a display panel configured to display an image, a gate driver configured to supply gate signals to the display panel, a data driver connected with the display panel, and a timing controller configured to control the gate driver, wherein the timing controller controls an output type of the gate driver so that one gate signal of the gate signals is applied per one gate line or per at least two gate lines, based on an image applied from an external device.

    Infinitely Expandable Display Apparatus and Driving Method Thereof

    公开(公告)号:US20220208057A1

    公开(公告)日:2022-06-30

    申请号:US17522749

    申请日:2021-11-09

    Abstract: An infinitely expandable display apparatus includes a set board outputting image data having a first resolution and a plurality of display circuits connected to one another through an interface circuit based on a cascading scheme to display the image data, each of the plurality of display circuits including an application specific integrated circuit (ASIC) embedded therein, wherein each of the plurality of display circuits includes a plurality of slave display circuits generating unit arrangement coordinate information based on a connection of the interface circuit and a master display circuit scaling the image data having the first resolution based on the unit arrangement coordinate information and transferring the scaled image data to the plurality of slave display circuits.

    Infinitely expandable display apparatus and driving method thereof

    公开(公告)号:US12008937B2

    公开(公告)日:2024-06-11

    申请号:US17522749

    申请日:2021-11-09

    Abstract: An infinitely expandable display apparatus includes a set board outputting image data having a first resolution and a plurality of display circuits connected to one another through an interface circuit based on a cascading scheme to display the image data, each of the plurality of display circuits including an application specific integrated circuit (ASIC) embedded therein, wherein each of the plurality of display circuits includes a plurality of slave display circuits generating unit arrangement coordinate information based on a connection of the interface circuit and a master display circuit scaling the image data having the first resolution based on the unit arrangement coordinate information and transferring the scaled image data to the plurality of slave display circuits.

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