Abstract:
A display apparatus can include a display panel including a first substrate and a second substrate, a color filter layer disposed on the first substrate, a plurality of gate lines and a plurality of data lines disposed on the second substrate to define a plurality of subpixels, a thin film transistor disposed in each of the plurality of subpixels on the second substrate, a common electrode and a pixel electrode disposed in each of the plurality of subpixels, and a light absorption layer disposed below each data line to absorb light incident from outside.
Abstract:
In one aspect, a display apparatus includes a display panel including a first substrate and a second substrate; a backlight unit facing the first substrate and configured to supply light to the display panel; a color filter layer on the first substrate; a plurality of gate lines and data lines on the second substrate configured to form a plurality of sub-pixels; a thin film transistor in each of the plurality of sub-pixels on the second substrate; a pixel electrode and a common electrode in each of the plurality of sub-pixels; a common line on the second substrate to apply an signal to the common electrode; and a light shielding layer under the common line. The light shielding layer includes a first light shielding layer configured to absorb the light and a second light shielding layer made of a metal.
Abstract:
An array substrate for a liquid crystal display device and method of manufacturing the same are provided. The array substrate includes: a plurality of paired gate lines at a first distance from each other at a boundary between adjacent first regions on a substrate, including a display area including a plurality of first regions, each including two adjacent pixel regions, a gate insulating layer on the gate lines and including a gate contact hole exposing each of the gate lines, a plurality of data lines crossing the paired gate lines, the first regions located at each crossing, an auxiliary gate line parallel with the data lines and at a boundary between the two adjacent two pixel regions, and a thin film transistor in each of the pixel regions and connected to corresponding gate and data lines, wherein the auxiliary gate line contacts the corresponding gate line through the hole.