公开(公告)号：US20190035872A1

公开(公告)日：2019-01-31

申请号：US16019379

申请日：2018-06-26

Applicant: LG Display Co., Ltd.

Inventor： Hyunchul UM ,  JinHwan KIM ,  YeongHo YUN ,  JunHo YEO ,  JeongMin BAE ,  Seokhwan CHOI

IPC: H01L27/32 ,  H01L51/00 ,  H01L51/52

CPC classification number: H01L27/3276 ,  G09G3/3225 ,  G09G2300/0426 ,  H01L27/3246 ,  H01L27/3248 ,  H01L27/3258 ,  H01L51/0097 ,  H01L51/5212 ,  H01L51/5253 ,  H01L51/5265 ,  H01L2251/5338

Abstract: A display device is disclosed, which may increase the number of lines arranged in a bending area and at the same time may minimize a crack generated in the bending area. The display device comprises a substrate including a display area on which pixels area arranged, and a non-display area surrounding the display area, provided with a bending within the non-display area; a plurality of first lines arranged in the bending area of the substrate and electrically connected with the pixels; a first organic film arranged on the first lines; a plurality of second lines arranged on the first organic film in the bending area of the substrate and electrically connected with the pixels; and a second organic film arranged on the second lines, wherein at least one of the first organic film and the second organic film is provided with an open area.

公开(公告)号：US20170169757A1

公开(公告)日：2017-06-15

申请号：US15371985

申请日：2016-12-07

Applicant: LG DISPLAY CO., LTD.

Inventor： Byungil KIM ,  Seokhwan CHOI

IPC: G09G3/20 ,  G11C19/28

CPC classification number: G09G3/2092 ,  G09G3/20 ,  G09G2300/0408 ,  G09G2300/043 ,  G09G2300/0809 ,  G09G2300/0819 ,  G09G2310/0267 ,  G09G2310/0286 ,  G09G2310/0291 ,  G11C19/28

Abstract: Provided are a gate driving circuit and a display device including the same. The gate driving circuit according to an embodiment includes a shift register including a plurality of stages. An nth stage of the stages includes a latch control circuit including a first NMOS transistor connected to a QB node, a second NMOS transistor connected to a Q node, and a third NMOS transistor having a gate electrode to which a first clock is input and connected to the first and second NMOS transistors, where n is a positive integer. A latch is connected between the Q and QB nodes. A transmission gate is connected to the Q and QB nodes. In the gate driving circuit, output signals of a previous stage and a following stage are controlled so as to be synchronized with the first clock to suppress a glitch.