公开(公告)号：US08745558B1

公开(公告)日：2014-06-03

申请号：US13755869

申请日：2013-01-31

Applicant: LSI Corporation

Inventor： Joseph Garofalo ,  Barry L. Bartholomew ,  Mujiang Luo ,  You Xin Rao

IPC: G06F17/50

CPC classification number: G06F17/505 ,  G06F17/5045

Abstract: A method is provided for designing an integrated circuit. The method includes generating a net list of an integrated circuit design, wherein the net list includes one or more component cells selected from a cell library. The component cells include transmission gate logic cells and sourcing cells that drive the transmission gate logic cells. Each transmission gate logic cell has an associated timing model with a timing characteristic defined as a function of a driving strength attribute of a sourcing cell used to characterize the transmission gate logic cell. The method further includes auditing the net list to determine if a given sourcing cell in the integrated circuit design has a sufficient driving strength based at least on the driving strength attribute of a transmission gate logic cell being driven by the given sourcing cell.

Abstract translation: 提供了一种用于设计集成电路的方法。 该方法包括生成集成电路设计的网络列表，其中网络列表包括从单元库选择的一个或多个组件单元。 组件单元包括传输门逻辑单元和驱动传输门逻辑单元的源单元。 每个传输门逻辑单元具有相关联的定时模型，定时特性被定义为用于表征传输门逻辑单元的源单元的驱动强度属性的函数。 该方法还包括审核网络列表以确定集成电路设计中的给定采购单元是否具有足够的驱动强度，至少基于由给定采购单元驱动的传输门逻辑单元的驱动强度属性。