公开(公告)号：US08724423B1

公开(公告)日：2014-05-13

申请号：US13712782

申请日：2012-12-12

Applicant: LSI Corporation

Inventor： Ting Zhou ,  Sheng Liu

IPC: G11C7/00 ,  G11C7/10 ,  G11C7/22 ,  G11C8/16 ,  G06F12/00 ,  G06F13/00 ,  G11C11/412 ,  G11C11/413 ,  G06F9/38 ,  G06F11/20

CPC classification number: G11C8/12 ,  G11C7/1075

Abstract: A memory operative to provide concurrent two-port read and two-port write access functionality includes a memory array comprising first and second pluralities of single-port memory cells organized into a plurality of rows of memory banks, and multiple checksum modules. The second plurality of memory cells are operative as spare memory banks. Each of the checksum modules is associated with a corresponding one of the rows of memory banks. The memory further includes a first controller and multiple mapping tables. The first controller and at least a portion of the first and second pluralities of memory cells enable the memory array to support two-port read or single-port write operations. A second controller is operative to receive read and write access requests, and to map logical and spare memory bank identifiers to corresponding physical memory bank identifiers via the mapping tables to thereby emulate concurrent two-port read and two-port write access functionality.

Abstract translation: 可操作以提供并发双端口读取和双端口写入访问功能的存储器包括存储器阵列，其包括组织成多行存储体的第一和第二多个单端口存储器单元，以及多个校验和模块。 第二组多个存储单元作为备用存储体来操作。 校验和模块中的每一个都与相应的一行存储体相关联。 存储器还包括第一控制器和多个映射表。 第一控制器和第一和第二多个存储器单元的至少一部分使得存储器阵列能够支持双端口读或单端口写操作。 第二控制器用于接收读取和写入访问请求，并且经由映射表将逻辑和备用存储体标识符映射到对应的物理存储器组标识符，从而模拟并发的双端口读取和双端口写入访问功能。

公开(公告)号：US20140177324A1

公开(公告)日：2014-06-26

申请号：US13725028

申请日：2012-12-21

Applicant: LSI CORPORATION

Inventor： Sheng Liu ,  Ting Zhou

IPC: G11C8/16 ,  G11C11/00

CPC classification number: G11C8/16

Abstract: A storage device provides single-port read multiple-port write functionality and includes first and second memory arrays and a controller. The first memory array includes first and second single-port memory cells. The second single-port memory cell stores data in response to a memory access conflict associated with the first single-port memory cell. The second memory array stores location information associated with data stored in the first and second single-port memory cells. The controller is operatively coupled to the first and second memory arrays, and resolves the memory access conflict by determining locations to store data in the first and second single-port memory cells to thereby avoid a collision between concurrent memory accesses to the first single-port memory cell in response to the memory access conflict. The controller determines locations to store data in the first and second single-port memory cells based on the location information.

Abstract translation: 存储设备提供单端口读取多端口写入功能，并且包括第一和第二存储器阵列和控制器。 第一存储器阵列包括第一和第二单端口存储器单元。 响应于与第一单端口存储器单元相关联的存储器访问冲突，第二单端口存储器单元存储数据。 第二存储器阵列存储与存储在第一和第二单端口存储器单元中的数据相关联的位置信息。 控制器可操作地耦合到第一和第二存储器阵列，并且通过确定在第一和第二单端口存储器单元中存储数据的位置来解决存储器访问冲突，从而避免在对第一单端口的并行存储器访问之间的冲突 内存单元响应内存访问冲突。 控制器基于位置信息确定在第一和第二单端口存储器单元中存储数据的位置。

公开(公告)号：US08923089B2

公开(公告)日：2014-12-30

申请号：US13725028

申请日：2012-12-21

Applicant: LSI Corporation

Inventor： Sheng Liu ,  Ting Zhou

IPC: G11C11/406 ,  G11C8/16 ,  G11C11/00

CPC classification number: G11C8/16

Abstract: A storage device provides single-port read multiple-port write functionality and includes first and second memory arrays and a controller. The first memory array includes first and second single-port memory cells. The second single-port memory cell stores data in response to a memory access conflict associated with the first single-port memory cell. The second memory array stores location information associated with data stored in the first and second single-port memory cells. The controller is operatively coupled to the first and second memory arrays, and resolves the memory access conflict by determining locations to store data in the first and second single-port memory cells to thereby avoid a collision between concurrent memory accesses to the first single-port memory cell in response to the memory access conflict. The controller determines locations to store data in the first and second single-port memory cells based on the location information.

Abstract translation: 存储设备提供单端口读取多端口写入功能，并且包括第一和第二存储器阵列和控制器。 第一存储器阵列包括第一和第二单端口存储器单元。 响应于与第一单端口存储器单元相关联的存储器访问冲突，第二单端口存储器单元存储数据。 第二存储器阵列存储与存储在第一和第二单端口存储器单元中的数据相关联的位置信息。 控制器可操作地耦合到第一和第二存储器阵列，并且通过确定在第一和第二单端口存储器单元中存储数据的位置来解决存储器访问冲突，从而避免在对第一单端口的并行存储器访问之间的冲突 内存单元响应内存访问冲突。 控制器基于位置信息确定在第一和第二单端口存储器单元中存储数据的位置。