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    System and Method for Providing a High-Speed Message Passing Interface for Barrier Operations in a Multi-Tiered Full-Graph Interconnect Architecture
    1.
    发明申请
    System and Method for Providing a High-Speed Message Passing Interface for Barrier Operations in a Multi-Tiered Full-Graph Interconnect Architecture 有权
    在多层全图互连架构中提供用于屏障操作的高速消息传递接口的系统和方法

    公开(公告)号：US20090063880A1

    公开(公告)日：2009-03-05

    申请号：US11845225

    申请日：2007-08-27

    申请人： Lakshminarayana B Arimilli ,  Ravi K. Arimilli ,  Ramakrishnan Rajamony

    发明人： Lakshminarayana B Arimilli ,  Ravi K. Arimilli ,  Ramakrishnan Rajamony

    IPC分类号： G06F9/46 ,  G06F1/32

    CPC分类号： G06F9/5088

    摘要： A method, computer program product, and system are provided performing a Message Passing Interface (MPI) job. A first processor chip receives a set of arrival signals from a set of processor chips executing tasks of the MPI job in the data processing system. The arrival signals identify when a processor chip executes a synchronization operation for synchronizing the tasks for the MPI job. Responsive to receiving the set of arrival signals from the set of processor chips, the first processor chip identifies a fastest processor chip of the set of processor chips whose arrival signal arrived first. An operation of the fastest processor chip is modified based on the identification of the fastest processor chip. The set of processor chips comprises processor chips that are in one of a same processor book or a different processor book of the data processing system.

    摘要翻译： 提供了执行消息传递接口（MPI）作业的方法，计算机程序产品和系统。 第一处理器芯片从数据处理系统中执行MPI作业的任务的一组处理器芯片接收一组到达信号。 到达信号确定处理器芯片何时执行用于同步MPI作业任务的同步操作。 响应于从该组处理器芯片接收到一组到达信号，第一处理器芯片标识出到达信号到达第一个处理器芯片集合中最快的处理器芯片。 基于最快处理器芯片的识别，修改最快处理器芯片的操作。 该组处理器芯片包括位于数据处理系统的相同处理器簿或不同处理器簿之一中的处理器芯片。