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1.发明授权Hardware based dynamic load balancing of message passing interface tasks by modifying tasks 失效基于硬件的动态负载平衡消息传递接口任务通过修改任务公开(公告)号：US08312464B2
公开(公告)日：2012-11-13
申请号：US11846168
申请日：2007-08-28
IPC分类号： G06F9/46
CPC分类号： G06F9/5083 , G06F9/522
摘要： Mechanisms are provided for providing hardware based dynamic load balancing of message passing interface (MPI) tasks by modifying tasks. Mechanisms for adjusting the balance of processing workloads of the processors executing tasks of an MPI job are provided so as to minimize wait periods for waiting for all of the processors to call a synchronization operation. Each processor has an associated hardware implemented MPI load balancing controller. The MPI load balancing controller maintains a history that provides a profile of the tasks with regard to their calls to synchronization operations. From this information, it can be determined which processors should have their processing loads lightened and which processors are able to handle additional processing loads without significantly negatively affecting the overall operation of the parallel execution system. Thus, operations may be performed to shift workloads from the slowest processor to one or more of the faster processors.
摘要翻译： 提供了通过修改任务来提供消息传递接口（MPI）任务的基于硬件的动态负载平衡的机制。 提供了用于调整执行MPI作业任务的处理器的处理工作负载的平衡的机制，以便最小化等待所有处理器调用同步操作的等待时间。 每个处理器都有一个相关的硬件实现的MPI负载平衡控制器。 MPI负载平衡控制器维护一个历史记录，提供任务关于其对同步操作的调用的简档。 根据该信息，可以确定哪些处理器应该减轻其处理负载，哪些处理器能够处理额外的处理负载，而不会对并行执行系统的整体操作产生显着的负面影响。 因此，可以执行操作以将工作负载从最慢处理器转移到一个或多个较快处理器。
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2.发明授权公开(公告)号：US07958182B2
公开(公告)日：2011-06-07
申请号：US11845223
申请日：2007-08-27
IPC分类号： G06F15/16
CPC分类号： G06F15/17381
摘要： A mechanism is provided for performing collective operations. In hardware of a parent processor in a first processor book, a number of other processors are determined in a same or different processor book of the data processing system that is needed to execute the collective operation, thereby establishing a plurality of processors comprising the parent processor and the other processors. In hardware of the parent processor, the plurality of processors are logically arranged as a plurality of nodes in a hierarchical structure. The collective operation is transmitted to the plurality of processors based on the hierarchical structure. In hardware of the parent processor, results are received from the execution of the collective operation from the other processors, a final result is generated of the collective operation based on the received results, and the final result is output.
摘要翻译： 提供了一种用于执行集体操作的机制。 在第一处理器书中的母处理器的硬件中，在执行集体操作所需的数据处理系统的相同或不同的处理器簿中确定多个其他处理器，由此建立多个处理器，其包括母处理器 和其他处理器。 在母处理器的硬件中，多个处理器在逻辑上被布置为分层结构中的多个节点。 基于层次结构将集体操作发送到多个处理器。 在母处理器的硬件中，从其他处理器的集体操作的执行中接收到结果，基于接收到的结果生成集合操作的最终结果，并输出最终结果。
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3.发明授权公开(公告)号：US07904590B2
公开(公告)日：2011-03-08
申请号：US11845215
申请日：2007-08-27
IPC分类号： G06F15/173
CPC分类号： G06F15/17381
摘要： A mechanism is provided for routing information through the data processing system. Data is received at a source processor within a set of processors that is to be transmitted to a destination processor, where the data includes address information. A first determination is performed as to whether the destination processor is within a same processor book as the source processor based on the address information. A second determination is performed as to whether the destination processor is within a same supernode as the source processor based on the address information if the destination processor is not within the same processor book. A routing path is identified for the data based on results of the first determination, the second determination, and one or more routing table data structures. The data is then transmitted from the source processor along the identified routing path toward the destination processor.
摘要翻译： 提供了一种通过数据处理系统路由信息的机制。 在要发送到目标处理器的一组处理器内的源处理器处接收数据，其中数据包括地址信息。 基于地址信息，执行目的地处理器是否在与处理器相同的处理器簿内的第一确定。 如果目的地处理器不在相同的处理器书中，则基于地址信息来执行关于目的地处理器是否在与源处理器相同的超级节点内的第二确定。 基于第一确定，第二确定和一个或多个路由表数据结构的结果，为数据识别路由路径。 然后将数据从源处理器沿着识别的路由路径发送到目的地处理器。
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4.发明申请Method for Hardware Based Dynamic Load Balancing of Message Passing Interface Tasks 失效基于硬件的消息传递接口任务的动态负载平衡方法公开(公告)号：US20090064165A1
公开(公告)日：2009-03-05
申请号：US11846119
申请日：2007-08-28
IPC分类号： G06F9/46
CPC分类号： G06F9/522 , G06F9/5083
摘要： A method for providing hardware based dynamic load balancing of message passing interface (MPI) tasks are provided. Mechanisms for adjusting the balance of processing workloads of the processors executing tasks of an MPI job are provided so as to minimize wait periods for waiting for all of the processors to call a synchronization operation. Each processor has an associated hardware implemented MPI load balancing controller. The MPI load balancing controller maintains a history that provides a profile of the tasks with regard to their calls to synchronization operations. From this information, it can be determined which processors should have their processing loads lightened and which processors are able to handle additional processing loads without significantly negatively affecting the overall operation of the parallel execution system. As a result, operations may be performed to shift workloads from the slowest processor to one or more of the faster processors.
摘要翻译： 提供了一种用于提供消息传递接口（MPI）任务的基于硬件的动态负载平衡的方法。 提供了用于调整执行MPI作业任务的处理器的处理工作负载的平衡的机制，以便最小化等待所有处理器调用同步操作的等待时间。 每个处理器都有一个相关的硬件实现的MPI负载平衡控制器。 MPI负载平衡控制器维护一个历史记录，提供任务关于其对同步操作的调用的简档。 根据该信息，可以确定哪些处理器应该减轻其处理负载，哪些处理器能够处理额外的处理负载，而不会对并行执行系统的整体操作产生显着的负面影响。 因此，可以执行操作以将工作负载从最慢的处理器转移到一个或多个更快的处理器。
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5.发明申请System and Method for Providing a Fully Non-Blocking Switch in a Supernode of a Multi-Tiered Full-Graph Interconnect Architecture 失效在多层全图互连架构的超节点中提供完全非阻塞开关的系统和方法公开(公告)号：US20090064140A1
公开(公告)日：2009-03-05
申请号：US11845211
申请日：2007-08-27
IPC分类号： G06F9/46
CPC分类号： G06F9/5061 , G06F15/17356 , G06F2209/5012 , H04L49/15 , H04L49/25
摘要： A method, computer program product, and system are provided for transmitting data from a first processor of a data processing system to a second processor of the data processing system. In one or more switches, a set of virtual channels is created, the one or more switches comprising, for each processor, a corresponding switch in the one or more switches. The data is transmitted from the first processor to the second processor through a path comprising a subset of processors of a set of processors in the data processing system. In each processor of the subset of processors, the data is stored in a virtual channel of a corresponding switch before transmitting the data to a next processor. The virtual channel of the corresponding switch in which the data is stored corresponds to a position of the processor in the path through which the data is transmitted.
摘要翻译： 提供了一种方法，计算机程序产品和系统，用于将数据从数据处理系统的第一处理器传送到数据处理系统的第二处理器。 在一个或多个交换机中，创建一组虚拟通道，一个或多个交换机为每个处理器包括一个或多个交换机中的相应开关。 数据通过包括数据处理系统中的一组处理器的处理器的子集的路径从第一处理器传送到第二处理器。 在处理器子集的每个处理器中，在将数据发送到下一个处理器之前，将数据存储在相应开关的虚拟通道中。 其中存储数据的相应交换机的虚拟通道对应于处理器在数据发送的路径中的位置。
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6.发明申请公开(公告)号：US20090063816A1
公开(公告)日：2009-03-05
申请号：US11845224
申请日：2007-08-27
CPC分类号： G06F15/17381
摘要： A method, computer program product, and system are provided for performing collective operations. In software executing on a parent processor in a first processor book, a number of other processors are determined in a same or different processor book of the data processing system that is needed to execute the collective operation, thereby establishing a plurality of processors comprising the parent processor and the other processors. In software executing on the parent processor, the plurality of processors are logically arranged as a plurality of nodes in a hierarchical structure. The collective operation is transmitted to the plurality of processors based on the hierarchical structure. In hardware of the parent processor, results are received from the execution of the collective operation from the other processors, a final result is generated of the collective operation based on the received results, and the final result is output.
摘要翻译： 提供了一种执行集体操作的方法，计算机程序产品和系统。 在第一处理器书中在母处理器上执行的软件中，在执行集体操作所需的数据处理系统的相同或不同的处理器簿中确定多个其他处理器，由此建立多个处理器，其包含该父 处理器和其他处理器。 在在母处理器上执行的软件中，多个处理器在逻辑上被布置为分层结构中的多个节点。 基于层次结构将集体操作发送到多个处理器。 在母处理器的硬件中，从其他处理器的集体操作的执行中接收到结果，基于接收到的结果生成集合操作的最终结果，并输出最终结果。
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7.发明申请Performing Setup Operations for Receiving Different Amounts of Data While Processors are Performing Message Passing Interface Tasks 审中-公开在处理器执行消息传递接口任务时，执行接收不同数据量的设置操作公开(公告)号：US20120266180A1
公开(公告)日：2012-10-18
申请号：US13524585
申请日：2012-06-15
IPC分类号： G06F9/52 , G06F15/173
CPC分类号： G06F9/522 , G06F9/5083
摘要： A system and method are provided for performing setup operations for receiving a different amount of data while processors are performing message passing interface (MPI) tasks. Mechanisms for adjusting the balance of processing workloads of the processors are provided so as to minimize wait periods for waiting for all of the processors to call a synchronization operation. An MPI load balancing controller maintains a history that provides a profile of the tasks with regard to their calls to synchronization operations. From this information, it can be determined which processors should have their processing loads lightened and which processors are able to handle additional processing loads without significantly negatively affecting the overall operation of the parallel execution system. As a result, setup operations may be performed while processors are performing MPI tasks to prepare for receiving different sized portions of data in a subsequent computation cycle based on the history.
摘要翻译： 提供了一种系统和方法，用于在处理器执行消息传递接口（MPI）任务时执行用于接收不同数量的数据的建立操作。 提供了用于调整处理器的处理工作负载的平衡的机制，以便最小化等待所有处理器调用同步操作的等待时间。 MPI负载平衡控制器维护一个历史记录，提供关于其对同步操作的调用的任务简档。 根据该信息，可以确定哪些处理器应该减轻其处理负载，哪些处理器能够处理额外的处理负载，而不会对并行执行系统的整体操作产生显着的负面影响。 结果，可以在处理器正在执行MPI任务以准备在基于历史的后续计算周期中接收不同大小的数据部分时执行设置操作。
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8.发明授权公开(公告)号：US08127300B2
公开(公告)日：2012-02-28
申请号：US11846119
申请日：2007-08-28
IPC分类号： G06F9/46 , G06F15/173
CPC分类号： G06F9/522 , G06F9/5083
摘要： Mechanisms for providing hardware based dynamic load balancing of message passing interface (MPI) tasks are provided. Mechanisms for adjusting the balance of processing workloads of the processors executing tasks of an MPI job are provided so as to minimize wait periods for waiting for all of the processors to call a synchronization operation. Each processor has an associated hardware implemented MPI load balancing controller. The MPI load balancing controller maintains a history that provides a profile of the tasks with regard to their calls to synchronization operations. From this information, it can be determined which processors should have their processing loads lightened and which processors are able to handle additional processing loads without significantly negatively affecting the overall operation of the parallel execution system. As a result, operations may be performed to shift workloads from the slowest processor to one or more of the faster processors.
摘要翻译： 提供了提供消息传递接口（MPI）任务的基于硬件的动态负载平衡的机制。 提供了用于调整执行MPI作业任务的处理器的处理工作负载的平衡的机制，以便最小化等待所有处理器调用同步操作的等待时间。 每个处理器都有一个相关的硬件实现的MPI负载平衡控制器。 MPI负载平衡控制器维护一个历史记录，提供任务关于其对同步操作的调用的简档。 根据该信息，可以确定哪些处理器应该减轻其处理负载，哪些处理器能够处理额外的处理负载，而不会对并行执行系统的整体操作产生显着的负面影响。 因此，可以执行操作以将工作负载从最慢的处理器转移到一个或多个更快的处理器。
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9.发明申请Host Fabric Interface (HFI) to Perform Global Shared Memory (GSM) Operations 失效主机结构接口（HFI）执行全局共享内存（GSM）操作公开(公告)号：US20090198918A1
公开(公告)日：2009-08-06
申请号：US12024397
申请日：2008-02-01
申请人： Lakshminarayana B. Arimilli , Ravi K. Arimilli , Robert S. Blackmore , Chulho Kim , Ramakrishnan Rajamony , William J. Starke , Hanhong Xue
发明人： Lakshminarayana B. Arimilli , Ravi K. Arimilli , Robert S. Blackmore , Chulho Kim , Ramakrishnan Rajamony , William J. Starke , Hanhong Xue
IPC分类号： G06F12/02
CPC分类号： G06F12/109 , G06F9/544
摘要： A data processing system enables global shared memory (GSM) operations across multiple nodes with a distributed EA-to-RA mapping of physical memory. Each node has a host fabric interface (HFI), which includes HFI windows that are assigned to at most one locally-executing task of a parallel job. The tasks perform parallel job execution, but map only a portion of the effective addresses (EAs) of the global address space to the local, real memory of the task's respective node. The HFI window tags all outgoing GSM operations (of the local task) with the job ID, and embeds the target node and HFI window IDs of the node at which the EA is memory mapped. The HFI window also enables processing of received GSM operations with valid EAs that are homed to the local real memory of the receiving node, while preventing processing of other received operations without a valid EA-to-RA local mapping.
摘要翻译： 数据处理系统通过物理内存的分布式EA-to-RA映射实现跨多个节点的全局共享存储（GSM）操作。 每个节点都有一个主机结构接口（HFI），它包括分配给并行作业最多一个本地执行任务的HFI窗口。 任务执行并行作业执行，但将全局地址空间的有效地址（EA）的一部分映射到任务相应节点的本地实际存储器。 HFI窗口使用作业ID对所有传出的GSM操作（本地任务）进行标记，并嵌入EA被映射到的节点的目标节点和HFI窗口ID。 HFI窗口还能够利用归属于接收节点的本地实际存储器的有效EA来处理接收的GSM操作，同时防止在没有有效的EA到RA本地映射的情况下处理其他接收到的操作。
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10.发明申请System and Method for Hardware Based Dynamic Load Balancing of Message Passing Interface Tasks By Modifying Tasks 失效基于硬件的动态负载平衡的系统和方法消息传递接口任务通过修改任务公开(公告)号：US20090064168A1
公开(公告)日：2009-03-05
申请号：US11846168
申请日：2007-08-28
IPC分类号： G06F9/46
CPC分类号： G06F9/5083 , G06F9/522
摘要： A system and method are provided for providing hardware based dynamic load balancing of message passing interface (MPI) tasks by modifying tasks. Mechanisms for adjusting the balance of processing workloads of the processors executing tasks of an MPI job are provided so as to minimize wait periods for waiting for all of the processors to call a synchronization operation. Each processor has an associated hardware implemented MPI load balancing controller. The MPI load balancing controller maintains a history that provides a profile of the tasks with regard to their calls to synchronization operations. From this information, it can be determined which processors should have their processing loads lightened and which processors are able to handle additional processing loads without significantly negatively affecting the overall operation of the parallel execution system. Thus, operations may be performed to shift workloads from the slowest processor to one or more of the faster processors.
摘要翻译： 提供了一种系统和方法，用于通过修改任务来提供消息传递接口（MPI）任务的基于硬件的动态负载平衡。 提供了用于调整执行MPI作业任务的处理器的处理工作负载的平衡的机制，以便最小化等待所有处理器调用同步操作的等待时间。 每个处理器都有一个相关的硬件实现的MPI负载平衡控制器。 MPI负载平衡控制器维护一个历史记录，提供任务关于其对同步操作的调用的简档。 根据该信息，可以确定哪些处理器应该减轻其处理负载，哪些处理器能够处理额外的处理负载，而不会对并行执行系统的整体操作产生显着的负面影响。 因此，可以执行操作以将工作负载从最慢处理器转移到一个或多个较快处理器。
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