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1.发明授权公开(公告)号：US08612797B2
公开(公告)日：2013-12-17
申请号：US11394585
申请日：2006-03-31
IPC分类号： G06F11/07
CPC分类号： G11C29/76
摘要： System and methods of selectively managing errors in memory modules. In an exemplary implementation, a method may include monitoring for persistent errors in the memory modules. The methods may also include mapping at least a portion of the memory modules to a spare memory cache only to obviate persistent errors. The method may also include initiating memory erasure on at least a portion of the memory modules only if insufficient cache lines are available in the spare memory cache.
摘要翻译： 有选择地管理存储器模块中的错误的系统和方法。 在示例性实现中，方法可以包括监视存储器模块中的持续错误。 所述方法还可以包括将至少一部分存储器模块映射到备用存储器高速缓存以避免持续错误。 该方法还可以包括仅当在备用存储器高速缓存中可用的高速缓存行不足时才启动存储器模块的至少一部分上的存储器擦除。
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2.发明授权公开(公告)号：US07694193B2
公开(公告)日：2010-04-06
申请号：US11685395
申请日：2007-03-13
CPC分类号： G06F12/0607
摘要： Systems and methods for implementing a stride value for memory are provided. One embodiment includes a system comprising a plurality of memory modules configured to store interleaved data in a plurality of memory storage units according to a predetermined interleave. The plurality of memory storage units can be defined by a memory range of consecutive addresses. The system also comprises a memory test device configured to access a portion of the plurality of memory storage units in a sequence that repeats according to a programmable stride value.
摘要翻译： 提供了用于实现存储器的步幅值的系统和方法。 一个实施例包括一种系统，其包括多个存储器模块，其被配置为根据预定的交错存储多个存储器存储单元中的交织数据。 多个存储器存储单元可以由连续地址的存储器范围来定义。 该系统还包括被配置为以按照可编程步幅值重复的顺序访问多个存储器单元的一部分的存储器测试设备。
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公开(公告)号：US07844868B2
公开(公告)日：2010-11-30
申请号：US12694718
申请日：2010-01-27
IPC分类号： G11C29/00
CPC分类号： G06F12/0607
摘要： Systems and methods for implementing a stride value for memory are provided. One embodiment relates to a system that includes a plurality of memory modules configured to store interleaved data in a plurality of memory storage units according to a predetermined interleave. A memory test device is configured to perform a memory test that accesses a portion of the plurality of memory storage units in a sequence according to a programmable stride value. The memory test device performs the memory test by writing test data to each of the memory storage units in the portion of the plurality of memory storage units and reading the test data from each of the memory storage units in the portion of the plurality of memory storage units.
摘要翻译： 提供了用于实现存储器的步幅值的系统和方法。 一个实施例涉及一种系统，其包括被配置为根据预定交错存储多个存储器存储单元中的交织数据的多个存储器模块。 存储器测试设备被配置为执行根据可编程步幅值以一序列访问所述多个存储器单元的一部分的存储器测试。 存储器测试设备通过将测试数据写入多个存储器单元的部分中的每个存储器存储单元并且从多个存储器存储器的部分中的每个存储器存储单元读取测试数据来执行存储器测试 单位。
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公开(公告)号：US20100131810A1
公开(公告)日：2010-05-27
申请号：US12694718
申请日：2010-01-27
IPC分类号： G11C29/10 , G06F11/07 , G06F11/263 , G06F12/00
CPC分类号： G06F12/0607
摘要： Systems and methods for implementing a stride value for memory are provided. One embodiment relates to a system that includes a plurality of memory modules configured to store interleaved data in a plurality of memory storage units according to a predetermined interleave. A memory test device is configured to perform a memory test that accesses a portion of the plurality of memory storage units in a sequence according to a programmable stride value. The memory test device performs the memory test by writing test data to each of the memory storage units in the portion of the plurality of memory storage units and reading the test data from each of the memory storage units in the portion of the plurality of memory storage units.
摘要翻译： 提供了用于实现存储器的步幅值的系统和方法。 一个实施例涉及一种系统，其包括被配置为根据预定交错存储多个存储器存储单元中的交织数据的多个存储器模块。 存储器测试设备被配置为执行根据可编程步幅值以一序列访问所述多个存储器单元的一部分的存储器测试。 存储器测试装置通过将测试数据写入多个存储器单元的部分中的每个存储器存储单元并且从多个存储器存储器的部分中的每个存储器存储单元读取测试数据来执行存储器测试 单位。
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5.发明申请公开(公告)号：US20080229035A1
公开(公告)日：2008-09-18
申请号：US11685395
申请日：2007-03-13
IPC分类号： G06F12/00
CPC分类号： G06F12/0607
摘要： Systems and methods for implementing a stride valise for memory are provided. One embodiment includes a system comprising a plurality of memory modules configured to store interleaved data in a plurality of memory storage units according to a predetermined interleave. The plurality of memory storage units can be defined by a memory range of consecutive addresses. The system also comprises a memory test device configured to access a portion of the plurality of memory storage units in a sequence that repeats according to a programmable stride value.
摘要翻译： 提供了用于实现用于存储器的步幅值的系统和方法。 一个实施例包括一种系统，其包括多个存储器模块，其被配置为根据预定的交错存储多个存储器存储单元中的交织数据。 多个存储器存储单元可以由连续地址的存储器范围来定义。 该系统还包括被配置为以按照可编程步幅值重复的顺序访问多个存储器单元的一部分的存储器测试设备。
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公开(公告)号：US08122291B2
公开(公告)日：2012-02-21
申请号：US12691512
申请日：2010-01-21
IPC分类号： G06F11/00
CPC分类号： G06F11/0766 , G06F11/0721 , G06F11/0793
摘要： Method and system of error logging. At least some of the illustrative embodiments are methods including detecting assertion of an error pin by a processor system, (comprising at least a main processor and a chipset, the assertion of the error pin an indication to reboot the processor system) the detecting by a reset circuit, notifying a management processor (distinct from the main processor) that the error pin is asserted (the notifying by the reset circuit), writing to a plurality of registers in the chipset (the writing by the management processor), de-asserting a reset pin of the main processor, and then executing by the main processor an error-handling code to generate an error log.
摘要翻译： 错误记录的方法和系统 说明性实施例中的至少一些是包括检测处理器系统的错误引脚的断言（包括至少主处理器和芯片组，断言错误引脚的重新引导处理器系统的指示）的方法， 复位电路，通知管理处理器（与主处理器不同），错误引脚被断言（由复位电路通知），写入芯片组中的多个寄存器（管理处理器的写入），取消断言 主处理器的复位引脚，然后由主处理器执行错误处理代码以生成错误日志。
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公开(公告)号：US08713350B2
公开(公告)日：2014-04-29
申请号：US12633648
申请日：2009-12-08
IPC分类号： G06F11/00
CPC分类号： G06F11/0793 , G06F11/0712 , G06F11/0766
摘要： A method of managing errors in a data processing system may involve at least one computer system. Each computer system may include a processor that executes an operating system, firmware, and system memory storing instructions for the operating system. A firmware error handler resident in the firmware may identify an error occurring in the computer system. The firmware error handler may determine whether the operating system is required to take an action in response to the error. If the operating system is not required to take an action in response to the error, the firmware error handler may create an error log accessible to the operating system appropriate to cause the operating system to take no action.
摘要翻译： 管理数据处理系统中的错误的方法可以涉及至少一个计算机系统。 每个计算机系统可以包括执行存储操作系统的指令的操作系统，固件和系统存储器的处理器。 驻留在固件中的固件错误处理程序可能会识别计算机系统中发生的错误。 固件错误处理程序可以确定操作系统是否需要采取响应错误的动作。 如果操作系统不需要采取措施来响应错误，则固件错误处理程序可能会创建适用于使操作系统不采取任何操作的操作系统可访问的错误日志。
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公开(公告)号：US20110179314A1
公开(公告)日：2011-07-21
申请号：US12691512
申请日：2010-01-21
IPC分类号： G06F11/07
CPC分类号： G06F11/0766 , G06F11/0721 , G06F11/0793
摘要： Method and system of error logging. At least some of the illustrative embodiments are methods including detecting assertion of an error pin by a processor system, (comprising at least a main processor and a chipset, the assertion of the error pin an indication to reboot the processor system) the detecting by a reset circuit, notifying a management processor (distinct from the main processor) that the error pin is asserted (the notifying by the reset circuit), writing to a plurality of registers in the chipset (the writing by the management processor), de-asserting a reset pin of the main processor, and then executing by the main processor an error-handling code to generate an error log.
摘要翻译： 错误记录的方法和系统 说明性实施例中的至少一些是包括检测处理器系统的错误引脚的断言（包括至少主处理器和芯片组，断言错误引脚的重新引导处理器系统的指示）的方法， 复位电路，通知管理处理器（与主处理器不同），错误引脚被断言（由复位电路通知），写入芯片组中的多个寄存器（管理处理器的写入），取消断言 主处理器的复位引脚，然后由主处理器执行错误处理代码以生成错误日志。
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9.发明授权公开(公告)号：US07103639B2
公开(公告)日：2006-09-05
申请号：US09730221
申请日：2000-12-05
申请人： Andrew C. Walton , Guy L. Kuntz
发明人： Andrew C. Walton , Guy L. Kuntz
IPC分类号： G06F15/167
CPC分类号： G06F15/177 , G06F9/4405 , G06F11/1417 , G06F11/1482 , G06F11/202
摘要： The present invention flexibly manages the formation of a partition from a plurality of independently executing cells (discrete hardware entities comprising system resources) in preparation for the instantiation of an operating system instance upon the partition. Specifically, the invention manages configuration activities that occur to transition from having individual cells acting independently, and having cells rendezvous, to having cells become interdependent to continue operations as a partition. The invention manages the partitioning forming process such that no single point of failure disrupts the process. Instead, the invention is implemented as a distributed application wherein individual cells independently execute instructions based upon respective copies of the complex profile (a “map” of the complex configuration). Also, the invention adapts to a degree of delay associated with certain cells becoming ready to join the formation or rendezvous process. The invention is able to cope with missing, unavailable, or otherwise malfunctioning cells. Additionally, the invention analyzes present cells to determine their compatibility and reject cells that are not compatible.
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公开(公告)号：US09645857B2
公开(公告)日：2017-05-09
申请号：US12641001
申请日：2009-12-17
CPC分类号： G06F9/5061 , G06F9/22 , G06F9/44
摘要： In accordance with at least some embodiments, a system includes a plurality of partitions, each partition having its own operating system (OS) and workload. The system also includes a plurality of resources assignable to the plurality of partitions. The system also includes management logic coupled to the plurality of partitions and the plurality of resources. The management logic is configured to set priority rules for each of the plurality of partitions based on user input. The management logic performs automated resource fault management for the resources assigned to the plurality of partitions based on the priority rules.
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