公开(公告)号：US07331032B2

公开(公告)日：2008-02-12

申请号：US11111908

申请日：2005-04-22

申请人： Laung-Terng (L. -T.) Wang ,  Augusli Kifli ,  Fei-Sheng Hsu ,  Xiaoqing Wen ,  Shih-Chia Kao ,  Shyh-Horng Lin ,  Hsin-Po Wang

发明人： Laung-Terng (L. -T.) Wang ,  Augusli Kifli ,  Fei-Sheng Hsu ,  Xiaoqing Wen ,  Shih-Chia Kao ,  Shyh-Horng Lin ,  Hsin-Po Wang

IPC分类号： G06F17/50

CPC分类号： G06F17/505 ,  G01R31/31704 ,  G01R31/318314 ,  G01R31/318364 ,  G01R31/318583 ,  G01R31/318594 ,  G06F17/5022 ,  G06F17/5027 ,  G06F17/5045 ,  G06F2217/14

摘要： A method and system to automate scan synthesis at register-transfer level (RTL). The method and system will produce scan HDL code modeled at RTL for an integrated circuit modeled at RTL. The method and system comprise computer-implemented steps of performing RTL testability analysis, clock-domain minimization, scan selection, test point selection, scan repair and test point insertion, scan replacement and scan stitching, scan extraction, interactive scan debug, interactive scan repair, and flush/random test bench generation. In addition, the present invention further comprises a method and system for hierarchical scan synthesis by performing scan synthesis module-by-module and then stitching these scanned modules together at top-level. The present invention further comprises integrating and verifying the scan HDL code with other design-for-test (DFT) HDL code, including boundary-scan and logic BIST (built-in self-test).