公开(公告)号：US07434126B2

公开(公告)日：2008-10-07

申请号：US11806098

申请日：2007-05-30

申请人： Laung-Terng Wang ,  Po-Ching Hsu ,  Xiaoqing Wen

发明人： Laung-Terng Wang ,  Po-Ching Hsu ,  Xiaoqing Wen

IPC分类号： G01R31/28 ,  G06F17/50

CPC分类号： G06F17/5022 ,  G01R31/31704 ,  G01R31/318552 ,  G01R31/318594 ,  G06F17/5031 ,  G06F17/505

摘要： A method and apparatus for providing ordered capture clocks to detect or locate faults within N clock domains and faults crossing any two clock domains in an integrated circuit or circuit assembly in self-test or scan-test mode, where N>1 and each domain has a plurality of scan cells. The method and apparatus allows generating and loading N pseudorandom or predetermined stimuli to all the scan cells within the N clock domains in the integrated circuit or circuit assembly during the shift operation, applying an ordered sequence of capture clocks to all the scan cells within the N clock domains during the capture operation, compacting or comparing N output responses of all the scan cells for analysis during the compact/compare operation, and repeating the above process until a predetermined limiting criteria is reached. A computer-aided design (CAD) system is further developed to realize the method and synthesize the apparatus.

摘要翻译： 一种用于提供有序捕获时钟以检测或定位N个时钟域内的故障的故障，以及跨越自检或扫描测试模式的集成电路或电路组件中的任何两个时钟域的故障，其中N≥1且每个域具有 多个扫描单元。 该方法和装置允许在移位操作期间将N个伪随机数或预定刺激生成并加载到集成电路或电路组件中的N个时钟域内的所有扫描单元，向N中的所有扫描单元应用捕获时钟的有序序列 捕获操作期间的时钟域，压缩或比较所有扫描单元的N个输出响应，以便在紧凑/比较操作期间进行分析，并重复上述处理，直到达到预定的限制标准。 进一步开发了计算机辅助设计（CAD）系统来实现该方法并综合了该装置。

公开(公告)号：US20070255988A1

公开(公告)日：2007-11-01

申请号：US11806098

申请日：2007-05-30

申请人： Laung-Terng Wang ,  Po-Ching Hsu ,  Xiaoqing Wen

发明人： Laung-Terng Wang ,  Po-Ching Hsu ,  Xiaoqing Wen

IPC分类号： G01R31/28

CPC分类号： G06F17/5022 ,  G01R31/31704 ,  G01R31/318552 ,  G01R31/318594 ,  G06F17/5031 ,  G06F17/505

摘要： A method and apparatus for providing ordered capture clocks to detect or locate faults within N clock domains and faults crossing any two clock domains in an integrated circuit or circuit assembly in self-test or scan-test mode, where N>1 and each domain has a plurality of scan cells. The method and apparatus allows generating and loading N pseudorandom or predetermined stimuli to all the scan cells within the N clock domains in the integrated circuit or circuit assembly during the shift operation, applying an ordered sequence of capture clocks to all the scan cells within the N clock domains during the capture operation, compacting or comparing N output responses of all the scan cells for analysis during the compact/compare operation, and repeating the above process until a predetermined limiting criteria is reached. A computer-aided design (CAD) system is further developed to realize the method and synthesize the apparatus.

摘要翻译： 一种用于提供有序捕获时钟以检测或定位N个时钟域内的故障的故障，以及跨越自检或扫描测试模式的集成电路或电路组件中的任何两个时钟域的故障，其中N≥1且每个域具有 多个扫描单元。 该方法和装置允许在移位操作期间将N个伪随机数或预定刺激生成并加载到集成电路或电路组件中的N个时钟域内的所有扫描单元，向N中的所有扫描单元应用捕获时钟的有序序列 捕获操作期间的时钟域，压缩或比较所有扫描单元的N个输出响应，以便在紧凑/比较操作期间进行分析，并重复上述处理，直到达到预定的限制标准。 进一步开发了计算机辅助设计（CAD）系统来实现该方法并综合了该装置。

公开(公告)号：US07779323B2

公开(公告)日：2010-08-17

申请号：US12222931

申请日：2008-08-20

申请人： Laung-Terng Wang ,  Po-Ching Hsu ,  Shih-Chia Kao ,  Meng-Chyi Lin ,  Hsin-Po Wang ,  Hao-Jan Chao ,  Xiaoqing Wen

发明人： Laung-Terng Wang ,  Po-Ching Hsu ,  Shih-Chia Kao ,  Meng-Chyi Lin ,  Hsin-Po Wang ,  Hao-Jan Chao ,  Xiaoqing Wen

IPC分类号： G01R31/28 ,  G06F11/00

CPC分类号： G06F17/5022 ,  G01R31/31704 ,  G01R31/318552 ,  G01R31/318594 ,  G06F17/5031 ,  G06F17/505

摘要： A method and apparatus for providing ordered capture clocks to detect or locate faults within N clock domains and faults crossing any two clock domains in an integrated circuit or circuit assembly in self-test or scan-test mode, where N>1 and each domain has a plurality of scan cells. The method and apparatus allows generating and loading N pseudorandom or predetermined stimuli to all the scan cells within the N clock domains in the integrated circuit or circuit assembly during the shift operation, applying an ordered sequence of capture clocks to all the scan cells within the N clock domains during the capture operation, compacting or comparing N output responses of all the scan cells for analysis during the compact/compare operation, and repeating the above process until a predetermined limiting criteria is reached. A computer-aided design (CAD) system is further developed to realize the method and synthesize the apparatus.

摘要翻译： 一种用于提供有序捕获时钟以检测或定位N个时钟域内的故障的故障，以及跨越自检或扫描测试模式的集成电路或电路组件中的任何两个时钟域的故障，其中N≥1且每个域具有 多个扫描单元。 该方法和装置允许在移位操作期间将N个伪随机数或预定刺激生成并加载到集成电路或电路组件中的N个时钟域内的所有扫描单元，向N中的所有扫描单元应用捕获时钟的有序序列 捕获操作期间的时钟域，压缩或比较所有扫描单元的N个输出响应，以便在紧凑/比较操作期间进行分析，并重复上述处理，直到达到预定的限制标准。 进一步开发了计算机辅助设计（CAD）系统来实现该方法并综合了该装置。

公开(公告)号：US07260756B1

公开(公告)日：2007-08-21

申请号：US11098703

申请日：2005-04-05

申请人： Laung-Terng Wang ,  Po-Ching Hsu ,  Xiaoqing Wen

发明人： Laung-Terng Wang ,  Po-Ching Hsu ,  Xiaoqing Wen

IPC分类号： G01R31/28 ,  G06F17/50

CPC分类号： G06F17/5022 ,  G01R31/31704 ,  G01R31/318552 ,  G01R31/318594 ,  G06F17/5031 ,  G06F17/505

摘要： A method and apparatus for providing ordered capture clocks to detect or locate faults within N clock domains and faults crossing any two clock domains in an integrated circuit or circuit assembly in self-test or scan-test mode, where N>1 and each domain has a plurality of scan cells. The method and apparatus allows generating and loading N pseudorandom or predetermined stimuli to all the scan cells within the N clock domains in the integrated circuit or circuit assembly during the shift operation, applying an ordered sequence of capture clocks to all the scan cells within the N clock domains during the capture operation, compacting or comparing N output responses of all the scan cells for analysis during the compact/compare operation, and repeating the above process until a predetermined limiting criteria is reached. A computer-aided design (CAD) system is further developed to realize the method and synthesize the apparatus.

摘要翻译： 一种用于提供有序捕获时钟以检测或定位N个时钟域内的故障的故障，以及跨越自检或扫描测试模式的集成电路或电路组件中的任何两个时钟域的故障，其中N≥1且每个域具有 多个扫描单元。 该方法和装置允许在移位操作期间将N个伪随机数或预定刺激生成并加载到集成电路或电路组件中的N个时钟域内的所有扫描单元，向N中的所有扫描单元应用捕获时钟的有序序列 捕获操作期间的时钟域，压缩或比较所有扫描单元的N个输出响应，以便在紧凑/比较操作期间进行分析，并重复上述处理，直到达到预定的限制标准。 进一步开发了计算机辅助设计（CAD）系统来实现该方法并综合了该装置。

公开(公告)号：US20070168803A1

公开(公告)日：2007-07-19

申请号：US11603085

申请日：2006-11-22

申请人： Laung-Terng Wang ,  Ming-Tung Chang ,  Hao-Jan Chao ,  Xiaoqing Wen ,  Po-Ching Hsu

发明人： Laung-Terng Wang ,  Ming-Tung Chang ,  Hao-Jan Chao ,  Xiaoqing Wen ,  Po-Ching Hsu

IPC分类号： G01R31/28

CPC分类号： G01R31/3185 ,  G01R31/31704 ,  G01R31/31705

摘要： A method and apparatus for inserting design-for-debug (DFD) circuitries in an integrated circuit to debug or diagnose DFT modules, including scan cores, memory BIST (built-in self-test) cores, logic BIST cores, and functional cores. The invention further comprises using a DFD controller for executing a plurality of DFD commands to debug or diagnosis the DFT modules embedded with the DFD circuitries. When used alone or combined together, these DFD commands will detect or locate physical failures in the DFT modules in the integrated circuit on an evaluation board or system using a low-cost DFT debugger. A computer-aided design (CAD) method is further developed to synthesize the DFD controller and DFD circuitries according to the IEEE 1149.1 Boundary-scan Std. The DFD controller supports, but is not limited to, the following DFD commands: RUN_SCAN, RUN_MBIST, RUN_LBIST, DBG_SCAN, DBG_MBIST, DBG_LBIST, DBG_FUNCTION, SELECT, SHIFT, SHIFT_CHAIN, CAPTURE, RESET, BREAK, RUN, STEP, and STOP.

公开(公告)号：US07058869B2

公开(公告)日：2006-06-06

申请号：US10762571

申请日：2004-01-23

申请人： Khader S. Abdel-Hafez ,  Xiaoqing Wen ,  Laung-Terng Wang ,  Po-Ching Hsu ,  Shih-Chia Kao ,  Hao-Jan Chao ,  Hsin-Po Wang

发明人： Khader S. Abdel-Hafez ,  Xiaoqing Wen ,  Laung-Terng Wang ,  Po-Ching Hsu ,  Shih-Chia Kao ,  Hao-Jan Chao ,  Hsin-Po Wang

IPC分类号： G01R31/3177 ,  G01R31/3181 ,  G01R31/3185

CPC分类号： G01R31/318572 ,  G01R31/31705 ,  G01R31/318591

摘要： A method and apparatus for debug, diagnosis, and/or yield improvement of a scan-based integrated circuit where scan chains embedded in a scan core 303 have no external access, such as the case when they are surrounded by pattern generators 302 and pattern compactors 305, using a DFT (design-for-test) technology such as Logic BIST (built-in self-test) or Compressed Scan. This invention includes an output-mask controller 301 and an output-mask network 304 to allow designers to mask off selected scan cells 311 from being compacted in a selected pattern compactor 305. This invention also includes an input chain-mask controller and an input-mask network for driving constant logic values into scan chain inputs of selected scan chains to allow designers to recover from scan chain hold time violations. Computer-aided design (CAD) methods are then proposed to automatically synthesize the output-mask controller 301, output-mask network 304, input chain-mask controller and input-mask network, and to further generate test patterns according to the synthesized scan-based integrated circuit.

摘要翻译： 一种用于基于扫描的集成电路的调试，诊断和/或产量改进的方法和装置，其中嵌入在扫描核心303中的扫描链没有外部访问，例如当它们被图案发生器302和模式压缩器包围时的情况 305，使用DFT（设计为测试）技术，如Logic BIST（内置自检）或压缩扫描。 本发明包括一个输出屏蔽控制器301和一个输出屏蔽网络304，以允许设计者掩蔽所选择的扫描单元311在选定的模式压实器305中被压缩。 本发明还包括输入链掩模控制器和输入掩模网络，用于将恒定逻辑值驱动到所选扫描链的扫描链输入中，以允许设计者从扫描链保持时间违规恢复。 然后提出了计算机辅助设计（CAD）方法来自动合成输出掩模控制器301，输出掩模网络304，输入链掩模控制器和输入掩模网络，并根据合成的扫描 - 基于集成电路。

公开(公告)号：US20090037786A1

公开(公告)日：2009-02-05

申请号：US12285225

申请日：2008-09-30

申请人： Laung-Terng Wang ,  Xiaoqing Wen ,  Khader S. Abdel-Hafez ,  Shyh-Horng Lin ,  Hsin-Po Wang ,  Ming-Tung Chang ,  Po-Ching Hsu ,  Shih-Chia Kao ,  Meng-Chyi Lin ,  Chi-Chan Hsu

发明人： Laung-Terng Wang ,  Xiaoqing Wen ,  Khader S. Abdel-Hafez ,  Shyh-Horng Lin ,  Hsin-Po Wang ,  Ming-Tung Chang ,  Po-Ching Hsu ,  Shih-Chia Kao ,  Meng-Chyi Lin ,  Chi-Chan Hsu

IPC分类号： G01R31/3177 ,  G06F11/25

CPC分类号： G06F11/27 ,  G01R31/318586 ,  G01R31/318594

摘要： A method and apparatus for testing or diagnosing faults in a scan-based integrated circuit using a unified self-test and scan-test technique. The method and apparatus comprises using a unified test controller to ease prototype debug and production test. The unified test controller further comprises using a capture clock generator and a plurality of domain clock generators each embedded in a clock domain to perform self-test or scan-test. The capture clocks generated by the capture clock generator are used to guide at-speed or reduced-speed self-test (or scan-test) within each clock domain. The frequency of these capture clocks can be totally unrelated to those of system clocks controlling the clock domains. This unified approach allows designers to test or diagnose stuck-type and non-stuck-type faults with a low-cost DFT (design-for-test) tester or a low-cost DFT debugger. A computer-aided design (CAD) method is further developed to realize the method and synthesize the apparatus.

摘要翻译： 一种用于使用统一的自检和扫描测试技术来测试或诊断基于扫描的集成电路中的故障的方法和装置。 该方法和装置包括使用统一的测试控制器来简化原型调试和生产测试。 统一的测试控制器还包括使用捕获时钟发生器和每个嵌入在时钟域中的多个域时钟发生器来执行自检或扫描测试。 由捕获时钟发生器产生的捕获时钟用于引导每个时钟域内的速度或速度自检（或扫描测试）。 这些捕获时钟的频率与控制时钟域的系统时钟的频率完全无关。 这种统一的方法允许设计人员使用低成本DFT（设计测试）测试仪或低成本DFT调试器来测试或诊断卡住型和非卡住型故障。 进一步开发了计算机辅助设计（CAD）方法，实现了该方法并综合了该装置。

公开(公告)号：US07284175B2

公开(公告)日：2007-10-16

申请号：US11603085

申请日：2006-11-22

申请人： Laung-Terng Wang ,  Ming-Tung Chang ,  Hao-Jan Chao ,  Xiaoqing Wen ,  Po-Ching Hsu

发明人： Laung-Terng Wang ,  Ming-Tung Chang ,  Hao-Jan Chao ,  Xiaoqing Wen ,  Po-Ching Hsu

IPC分类号： G01R31/28

CPC分类号： G01R31/3185 ,  G01R31/31704 ,  G01R31/31705

摘要： A method and apparatus for inserting design-for-debug (DFD) circuitries in an integrated circuit to debug or diagnose DFT modules, including scan cores, memory BIST (built-in self-test) cores, logic BIST cores, and functional cores. The invention further comprises using a DFD controller for executing a plurality of DFD commands to debug or diagnosis the DFT modules embedded with the DFD circuitries. When used alone or combined together, these DFD commands will detect or locate physical failures in the DFT modules in the integrated circuit on an evaluation board or system using a low-cost DFT debugger. A computer-aided design (CAD) method is further developed to synthesize the DFD controller and DFD circuitries according to the IEEE 1149.1 Boundary-scan Std. The DFD controller supports, but is not limited to, the following DFD commands: RUN_SCAN, RUN_MBIST, RUN_LBIST, DBG_SCAN, DBG_MBIST, DBG_LBIST, DBG_FUNCTION, SELECT, SHIFT, SHIFT_CHAIN, CAPTURE, RESET, BREAK, RUN, STEP, and STOP.

公开(公告)号：US07451371B2

公开(公告)日：2008-11-11

申请号：US11151258

申请日：2005-06-14

申请人： Laung-Terng Wang ,  Xiaoqing Wen

发明人： Laung-Terng Wang ,  Xiaoqing Wen

IPC分类号： G01R31/28

CPC分类号： G01R31/318594 ,  G01R31/31704 ,  G01R31/318552 ,  G01R31/31858

摘要： A method and apparatus for providing ordered capture clocks to detect or locate faults within N clock domains and faults crossing any two clock domains in a scan-based integrated circuit or circuit assembly in self-test or scan-test mode, where N>1 and each domain has a plurality of scan cells. The method and apparatus will apply an ordered sequence of capture clocks to all scan cells within N clock domains where one or more capture clocks must contain one or more shift clock pulses during the capture operation. A computer-aided design (CAD) method is further developed to realize the method and synthesize the apparatus. In order to further improve the circuit's fault coverage, a CAD method and apparatus are further developed to minimize the memory usage and generate scan patterns for full-scan and feed-forward partial-scan designs containing transparent storage cells, asynchronous set/reset signals, tri-state busses, and low-power gated clocks.

摘要翻译： 一种用于提供有序捕获时钟以检测或定位N个时钟域内的故障的方法和装置，以及在自检或扫描测试模式中跨过基于扫描的集成电路或电路组件中的任何两个时钟域的故障，其中N≥1和 每个域具有多个扫描单元。 该方法和装置将对N个时钟域内的所有扫描单元应用有序序列的捕获时钟，其中一个或多个捕获时钟在捕获操作期间必须包含一个或多个移位时钟脉冲。 进一步开发了计算机辅助设计（CAD）方法，实现了该方法并综合了该装置。 为了进一步改善电路的故障覆盖范围，进一步开发了一种CAD方法和装置，以最小化存储器使用并产生包含透明存储单元，异步设置/复位信号的全扫描和前馈部分扫描设计的扫描模式， 三态总线和低功率门控时钟。

公开(公告)号：US20050262409A1

公开(公告)日：2005-11-24

申请号：US10850460

申请日：2004-05-21

申请人： Laung-Terng Wang ,  Khader Abdel-Hafez ,  Xiaoqing Wen ,  Boryau Sheu ,  Shun-Miin Wang

发明人： Laung-Terng Wang ,  Khader Abdel-Hafez ,  Xiaoqing Wen ,  Boryau Sheu ,  Shun-Miin Wang

IPC分类号： G01R31/28 ,  G01R31/30 ,  G01R31/3183 ,  G01R31/3185 ,  G06F11/00

CPC分类号： G01R31/318594 ,  G01R31/3008 ,  G01R31/318342 ,  G01R31/318364 ,  G01R31/318563

摘要： A method for generating stimuli and test responses for testing faults in a scan-based integrated circuit in a selected scan-test mode or a selected self-test mode, the scan-based integrated circuit containing a plurality of scan chains, N clock domains, and C cross-clock domain blocks, each scan chain comprising multiple scan cells coupled in series, each clock domain having one capture clock, each cross-clock domain block comprising a combinational logic network. The method comprises compiling the scan-based integrated circuit into a sequential circuit model; specifying input constraints on the scan-based integrated circuit during a shift and capture operation; specifying a clock grouping to map the N clock domains into G clock domain groups, where N>G>1; transforming the sequential circuit model into an equivalent combinational circuit model according to the input constraints and the clock grouping; and generating the stimuli and test responses on the equivalent combinational circuit model according to the input constraints.

摘要翻译： 一种用于产生用于以选定的扫描测试模式或选定的自测模式测试基于扫描的集成电路中的故障的刺激和测试响应的方法，所述基于扫描的集成电路包含多个扫描链，N个时钟域， 和C个跨时钟域块，每个扫描链包括串联耦合的多个扫描单元，每个时钟域具有一个捕获时钟，每个交叉时钟域块包括组合逻辑网络。 该方法包括将基于扫描的集成电路编译成顺序电路模型; 在移位和捕获操作期间指定基于扫描的集成电路的输入约束; 指定时钟分组以将N个时钟域映射到G个时钟域组，其中N> G> 1; 根据输入约束和时钟分组将顺序电路模型转换为等效组合电路模型; 并根据输入约束在等效组合电路模型上产生刺激和测试响应。