公开(公告)号：US20070192567A1

公开(公告)日：2007-08-16

申请号：US11674924

申请日：2007-02-14

申请人： Lawrence Hudepohl ,  Darren Jones ,  Radhika Thekkath ,  Franz Treue

发明人： Lawrence Hudepohl ,  Darren Jones ,  Radhika Thekkath ,  Franz Treue

IPC分类号： G06F15/00

CPC分类号： G06F9/3885 ,  G06F9/3836 ,  G06F9/3855 ,  G06F9/3857 ,  G06F9/3859

摘要： A configurable coprocessor interface between a central processing unit (CPU) and a coprocessor is provided. The coprocessor interface has an instruction transfer signal group for transferring different instruction types from the CPU to the coprocessor, sequentially or in parallel, a busy signal group, for allowing the coprocessor to signal the CPU that it cannot receive a transfer of one or more of the different instruction types, and an instruction order signal group for indicating to the coprocessor a relative execution order for multiple instructions that are transferred in parallel. In addition, the coprocessor interface includes separate data transfer signal groups for data being transferred from the CPU to the coprocessor, and for data being transferred from the coprocessor to the CPU, along with a data order signal group for indicating a relative order of data (if transferred out-of-order). The interface further includes signal designations which allow for multiple issue groups between the CPU and one or more coprocessors.

摘要翻译： 提供了中央处理单元（CPU）和协处理器之间的可配置协处理器接口。 协处理器接口具有用于将不同指令类型从CPU向协处理器顺序或并行传送到忙信号组的指令传送信号组，用于允许协处理器向CPU发信号通知其不能接收一个或多个 不同的指令类型和用于向协处理器指示并行传送的多个指令的相对执行顺序的指令顺序信号组。 此外，协处理器接口包括用于从CPU传输到协处理器的数据的分离的数据传输信号组，以及用于指示数据的相对顺序的数据顺序信号组（从协处理器传送到CPU） 如果无序转移）。 该接口还包括允许CPU和一个或多个协处理器之间的多个问题组的信号指定。

公开(公告)号：US20060259738A1

公开(公告)日：2006-11-16

申请号：US11380925

申请日：2006-04-29

申请人： Lawrence Hudepohl ,  Darren Jones ,  Radhika Thekkath ,  Franz Treue

发明人： Lawrence Hudepohl ,  Darren Jones ,  Radhika Thekkath ,  Franz Treue

IPC分类号： G06F15/00

CPC分类号： G06F9/3885 ,  G06F9/3836 ,  G06F9/3855 ,  G06F9/3857 ,  G06F9/3859

摘要： A configurable coprocessor interface between a central processing unit (CPU) and a coprocessor is provided. The coprocessor interface has an instruction transfer signal group for transferring different instruction types from the CPU to the coprocessor, sequentially or in parallel, a busy signal group, for allowing the coprocessor to signal the CPU that it cannot receive a transfer of one or more of the different instruction types, and an instruction order signal group for indicating to the coprocessor a relative execution order for multiple instructions that are transferred in parallel. In addition, the coprocessor interface includes separate data transfer signal groups for data being transferred from the CPU to the coprocessor, and for data being transferred from the coprocessor to the CPU, along with a data order signal group for indicating a relative order of data (if transferred out-of-order). The interface further includes signal designations which allow for multiple issue groups between the CPU and one or more coprocessors.

摘要翻译： 提供了中央处理单元（CPU）和协处理器之间的可配置协处理器接口。 协处理器接口具有用于将不同指令类型从CPU向协处理器顺序或并行传送到忙信号组的指令传送信号组，用于允许协处理器向CPU发信号通知其不能接收一个或多个 不同的指令类型和用于向协处理器指示并行传送的多个指令的相对执行顺序的指令顺序信号组。 此外，协处理器接口包括用于从CPU传输到协处理器的数据的分离的数据传输信号组，以及用于指示数据的相对顺序的数据顺序信号组（从协处理器传送到CPU） 如果无序转移）。 该接口还包括允许CPU和一个或多个协处理器之间的多个问题组的信号指定。

公开(公告)号：US20050038975A1

公开(公告)日：2005-02-17

申请号：US10923584

申请日：2004-08-21

申请人： Lawrence Hudepohl ,  Darren Jones ,  Radhika Thekkath ,  Franz Treue

发明人： Lawrence Hudepohl ,  Darren Jones ,  Radhika Thekkath ,  Franz Treue

IPC分类号： G06F9/38 ,  G06F15/00

CPC分类号： G06F9/3885 ,  G06F9/3836 ,  G06F9/3855 ,  G06F9/3857 ,  G06F9/3859

摘要： A configurable coprocessor interface between a central processing unit (CPU) and a coprocessor is provided. The coprocessor interface has an instruction transfer signal group for transferring different instruction types from the CPU to the coprocessor, sequentially or in parallel, a busy signal group, for allowing the coprocessor to signal the CPU that it cannot receive a transfer of one or more of the different instruction types, and an instruction order signal group for indicating to the coprocessor a relative execution order for multiple instructions that are transferred in parallel. In addition, the coprocessor interface includes separate data transfer signal groups for data being transferred from the CPU to the coprocessor, and for data being transferred from the coprocessor to the CPU, along with a data order signal group for indicating a relative order of data (if transferred out-of-order). The interface further includes signal designations which allow for multiple issue groups between the CPU and one or more coprocessors.

摘要翻译： 提供了中央处理单元（CPU）和协处理器之间的可配置协处理器接口。 协处理器接口具有用于将不同指令类型从CPU向协处理器顺序或并行传送到忙信号组的指令传送信号组，用于允许协处理器向CPU发信号通知其不能接收一个或多个 不同的指令类型和用于向协处理器指示并行传送的多个指令的相对执行顺序的指令顺序信号组。 此外，协处理器接口包括用于从CPU传输到协处理器的数据的分离的数据传输信号组，以及用于指示数据的相对顺序的数据顺序信号组（从协处理器传送到CPU） 如果无序转移）。 该接口还包括允许CPU和一个或多个协处理器之间的多个问题组的信号指定。