公开(公告)号：US20120131523A1

公开(公告)日：2012-05-24

申请号：US12950371

申请日：2010-11-19

申请人： Lee-Chung LU ,  Yun-Han LEE ,  Wei-Li CHEN ,  Tan-Li CHOU ,  Kheng-Guan TAN ,  Shi-Hung WANG

发明人： Lee-Chung LU ,  Yun-Han LEE ,  Wei-Li CHEN ,  Tan-Li CHOU ,  Kheng-Guan TAN ,  Shi-Hung WANG

IPC分类号： G06F17/50

CPC分类号： G06F17/505 ,  G06F17/5022 ,  G06F2217/02 ,  G06F2217/66

摘要： The present application discloses a method of generating an intellectual property (IP) block design kit including an IP block circuit design and a system-level characteristics table for manufacturing an integrated circuit. According at least one embodiment, the IP block circuit design is generated. The IP block circuit design is simulated based on predetermined configuration sets, and each configuration set has manufacturing options and/or operating conditions. A plurality of system-level models for the predetermined configuration sets are generated based on the simulation of the IP block circuit design. The system-level characteristics table is generated by arranging the predetermined configuration sets and the system-level models in compliance with a system-level characteristics table template of a system-level characteristics modeling device. Then the IP block circuit design and the system-level characteristics table are stored as the IP block design kit.

摘要翻译： 本申请公开了一种生成包括IP块电路设计和用于制造集成电路的系统级特性表的知识产权（IP）块设计套件的方法。 根据至少一个实施例，产生IP块电路设计。 IP块电路设计基于预定的配置集进行仿真，每个配置集都具有制造选项和/或操作条件。 基于IP块电​​路设计的仿真，生成用于预定配置集的多个系统级模型。 通过根据系统级特征建模设备的系统级特征表模板布置预定配置集和系统级模型来生成系统级特征表。 然后将IP块电路设计和系统级特性表存储为IP块设计工具包。