公开(公告)号：US06789248B1

公开(公告)日：2004-09-07

申请号：US10178401

申请日：2002-06-24

申请人： Lee-Chung Lu ,  Cliff Hou ,  Chia-Lin Cheng ,  Chung-Hsing Wang ,  Hsing-Chien Huang ,  Yee-Wen Chen ,  Tsui-Ping Wang

发明人： Lee-Chung Lu ,  Cliff Hou ,  Chia-Lin Cheng ,  Chung-Hsing Wang ,  Hsing-Chien Huang ,  Yee-Wen Chen ,  Tsui-Ping Wang

IPC分类号： G06F1750

CPC分类号： G06F17/5068

摘要： A method and system for the design of an electronic device adjusts the resistance and capacitance values employed in preliminary timing analysis during physical synthesis of the electronic device. The physical synthesis uses resistance and capacitance unit values to determine the listing of the component circuits. The resistance and capacitance unit values are calibrated by preliminarily placing the initially synthesized component circuits to create a listing describing physical locations of the component circuits within the electronic device. A preliminary routing of the interconnections is performed to create a listing describing a network of physical wire segments that form each interconnection of the component circuits. A timing analysis of the electronic device determines the delay created by the component circuit and the networks of physical wire segments. The time delay resulting from the physical interconnects is extracted from the timing analysis of the electronic device and from the timing estimate performed during the physical synthesis. The time delay of the physical interconnection from the timing analysis and the timing estimate performed during the physical synthesis is then compared. The resistance and capacitance unit values used during the timing synthesis are then adjusted. The calibration is repeatedly executed until time delay of the physical interconnection from the timing analysis and the timing estimate performed during the physical synthesis are correlated.

摘要翻译： 用于设计电子设备的方法和系统调节在电子设备的物理合成期间的初步时序分析中使用的电阻和电容值。 物理合成使用电阻和电容单位值来确定元件电路的列表。 电阻和电容单位值通过预先放置最初合成的组件电路来校准，以创建描述电子设备内的组件电路的物理位置的列表。 执行互连的初步路由以创建描述形成组件电路的每个互连的物理线段的网络的列表。 电子设备的定时分析确定由组件电路和物理线段网络产生的延迟。 从物理互连产生的时间延迟从电子设备的定时分析以及在物理合成期间执行的定时估计提取。 然后对来自定时分析的物理互连的时间延迟和在物理合成期间执行的定时估计进行比较。 然后调整在定时合成期间使用的电阻和电容单位值。 重复执行校准，直到来自定时分析的物理互连的时间延迟和在物理合成期间执行的定时估计相关。