公开(公告)号：US07469372B2

公开(公告)日：2008-12-23

申请号：US11381624

申请日：2006-05-04

申请人： Lewis Nardini ,  Alan D. Hales

发明人： Lewis Nardini ,  Alan D. Hales

IPC分类号： G01R31/28

CPC分类号： G01R31/318575

摘要： A scan sequenced initialization technique supplies a predefined power-on state to a device or module without using explicit reset input to the registers. This technique supplies a predefined pattern to parallel scan chains following power-on reset. The predefined pattern places the device or module in a architecturally specified reset state. The parallel scan chains are required for structural manufacturing test. Once the power-on reset scanning is complete, the power-on reset sequencer indicates completion of state initialization to other circuits.

摘要翻译： 扫描顺序初始化技术将预定义的开机状态提供给设备或模块，而不使用对寄存器的显式复位输入。 上电复位后，这种技术为并行扫描链提供预定义的模式。 预定义模式将设备或模块置于架构上指定的复位状态。 并行扫描链是结构制造测试所必需的。 一旦上电复位扫描完成，上电复位定序器就会指示完成其他电路的状态初始化。

公开(公告)号：US07039823B2

公开(公告)日：2006-05-02

申请号：US10422275

申请日：2003-04-24

申请人： Alan D. Hales ,  Anthony M. Hill

发明人： Alan D. Hales ,  Anthony M. Hill

IPC分类号： G06F1/12

CPC分类号： G06F1/24

摘要： An integrated circuit includes an external reset input, a clock input for receiving a clock signal and a reset signal sub-circuit including an internal reset output connected to other circuits of the integrated circuit. The reset signal sub-circuit immediately supplies an internal reset signal upon receipt of the external reset signal and ceases to supply the internal reset signal upon a next clock signal following ceasing to receive the external reset signal. This asynchronously forces combinational logic to a reset state upon receipt of the internal reset signal and synchronously forces sequential logic to a reset state upon receipt of a next clock signal.