公开(公告)号：US07272807B2

公开(公告)日：2007-09-18

申请号：US11071121

申请日：2005-03-02

申请人： Li Ding ,  Peivand Fallah Tehrani ,  Alireza Kasnavi

发明人： Li Ding ,  Peivand Fallah Tehrani ,  Alireza Kasnavi

IPC分类号： G06F17/50

CPC分类号： G06F17/5036 ,  G06F17/5031

摘要： An equivalent waveform for a distorted waveform used in timing and signal integrity analysis in the design of an integrated circuit is automatically generated. The equivalent waveform is produced by calculating the transition quantity of a first non-distorted waveform. The transition quantity is the amount of transition of the first non-distorted waveform that is required for the cell to produce an output waveform with a predetermined end voltage. The end point of the transition period for the distorted waveform is then determined based on when the distorted waveform has accumulated the same transition quantity. The equivalent waveform can then be formed by computing a second non-distorted waveform such that the end point of the transition period for the second non-distorted waveform coincides with the end point of the transition period for the distorted waveform.

摘要翻译： 自动生成在集成电路设计中用于定时和信号完整性分析的失真波形的等效波形。 通过计算第一非失真波形的转移量来产生等效波形。 转换量是单元格产生具有预定端电压的输出波形所需的第一非失真波形的转变量。 然后，基于失真波形累积相同过渡量的时间来确定失真波形的转换周期的终点。 然后可以通过计算第二非失真波形来形成等效波形，使得第二非失真波形的转换周期的终点与失真波形的过渡周期的终点重合。

公开(公告)号：US20070010981A1

公开(公告)日：2007-01-11

申请号：US11166659

申请日：2005-06-23

申请人： Li Ding ,  Peivand Fallah-Tehrani ,  Alireza Kasnavi

发明人： Li Ding ,  Peivand Fallah-Tehrani ,  Alireza Kasnavi

IPC分类号： G06F17/50

CPC分类号： G06F17/5031

摘要： A model for a circuit cell used in timing and signal integrity analysis in an integrated circuit design is automatically generated. A behavioral model, such as a gate current model is used in which the current in the circuit cell is determined as a function of the input voltage and the output voltage of the circuit cell as well as the history of at least one of the current, voltage, and charge values of the circuit cell. For example, the current in the circuit cell may be a function of the history of the current, which may be calculated incrementally using recursive convolution at each time step when using the model.

摘要翻译： 自动生成用于集成电路设计中的时序和信号完整性分析的电路单元的模型。 使用诸如栅极电流模型的行为模型，其中电路单元中的电流被确定为电路单元的输入电压和输出电压的函数以及电流单元中的至少一个的历史， 电压和电荷值。 例如，电路单元中的电流可以是电流的历史的函数，其可以在使用该模型时在每个时间步长处使用递归卷积来逐渐计算。

公开(公告)号：US08478573B2

公开(公告)日：2013-07-02

申请号：US11166659

申请日：2005-06-23

申请人： Li Ding ,  Peivand Fallah-Tehrani ,  Alireza Kasnavi

发明人： Li Ding ,  Peivand Fallah-Tehrani ,  Alireza Kasnavi

IPC分类号： G06F17/50

CPC分类号： G06F17/5031

摘要： A model for a circuit cell used in timing and signal integrity analysis in an integrated circuit design is automatically generated. A behavioral model, such as a gate current model is used in which the current in the circuit cell is determined as a function of the input voltage and the output voltage of the circuit cell as well as the history of at least one of the current, voltage, and charge values of the circuit cell. For example, the current in the circuit cell may be a function of the history of the current, which may be calculated incrementally using recursive convolution at each time step when using the model.

摘要翻译： 自动生成用于集成电路设计中的时序和信号完整性分析的电路单元的模型。 使用诸如栅极电流模型的行为模型，其中电路单元中的电流被确定为电路单元的输入电压和输出电压的函数以及电流单元中的至少一个的历史， 电压和电荷值。 例如，电路单元中的电流可以是电流的历史的函数，其可以在使用该模型时在每个时间步长处使用递归卷积来逐渐计算。

公开(公告)号：US20060200784A1

公开(公告)日：2006-09-07

申请号：US11071121

申请日：2005-03-02

申请人： Li Ding ,  Peivand Fallah-Tehrani ,  Alireza Kasnavi

发明人： Li Ding ,  Peivand Fallah-Tehrani ,  Alireza Kasnavi

IPC分类号： G06F17/50

CPC分类号： G06F17/5036 ,  G06F17/5031

摘要： An equivalent waveform for a distorted waveform used in timing and signal integrity analysis in the design of an integrated circuit is automatically generated. The equivalent waveform is produced by calculating the transition quantity of a first non-distorted waveform. The transition quantity is the amount of transition of the first non-distorted waveform that is required for the cell to produce an output waveform with a predetermined end voltage. The end point of the transition period for the distorted waveform is then determined based on when the distorted waveform has accumulated the same transition quantity. The equivalent waveform can then be formed by computing a second non-distorted waveform such that the end point of the transition period for the second non-distorted waveform coincides with the end point of the transition period for the distorted waveform.

摘要翻译： 自动生成在集成电路设计中用于定时和信号完整性分析的失真波形的等效波形。 通过计算第一非失真波形的转移量来产生等效波形。 转换量是单元格产生具有预定端电压的输出波形所需的第一非失真波形的转变量。 然后，基于失真波形累积相同过渡量的时间来确定失真波形的转换周期的终点。 然后可以通过计算第二非失真波形来形成等效波形，使得第二非失真波形的转换周期的终点与失真波形的过渡周期的终点重合。

公开(公告)号：US07962876B2

公开(公告)日：2011-06-14

申请号：US12263447

申请日：2008-10-31

申请人： Nahmsuk Oh ,  Peivand Fallah-Tehrani ,  Alireza Kasnavi

发明人： Nahmsuk Oh ,  Peivand Fallah-Tehrani ,  Alireza Kasnavi

IPC分类号： G06F17/50

CPC分类号： G06F17/5022 ,  G06F17/5031

摘要： Static timing and/or noise analysis are performed on a netlist of an integrated circuit, to estimate behavior of the netlist and to identify at least one violation by said behavior of a corresponding requirement thereon, such as setup time, hold time or bump height in a quiescent net. Thereafter, effect of engineering change order (ECO) to correct the violation are automatically analyzed, based on the layout, the parasitics, the timing and/or noise behavior, and the violation, followed by generation of a constraint on the behavior (called “ECO” constraint), such as a timing constraint and/or a noise constraint. Next, the ECO constraint is automatically used, e.g. in a place and route tool, to select an ECO repair technique, from several ECO repair techniques that can overcome the violation. The selected ECO repair technique is automatically applied to the layout, to generate a modified layout which does not have the violation.

摘要翻译： 静态时序和/或噪声分析在集成电路的网表上执行，以估计网表的行为，并通过其上的相应要求的所述行为识别至少一个违规，诸如建立时间，保持时间或突发高度 一个静止网。 此后，根据布局，寄生效应，时间安排和/或噪音行为以及违规行为自动分析工程变更单（ECO）对违规行为的影响，随后对行为产生约束（称为“ ECO“约束），诸如时序约束和/或噪声约束。 接下来，自动使用ECO约束。 在地方和路线工具中，选择一种ECO修复技术，从几种可以克服违规的ECO修复技术。 选择的ECO修复技术自动应用于布局，以生成不具有违规的修改的布局。

公开(公告)号：US07454731B2

公开(公告)日：2008-11-18

申请号：US11525578

申请日：2006-09-22

申请人： Nahmsuk Oh ,  Peivand Fallah-Tehrani ,  Alireza Kasnavi

发明人： Nahmsuk Oh ,  Peivand Fallah-Tehrani ,  Alireza Kasnavi

IPC分类号： G06F17/50

CPC分类号： G06F17/5022 ,  G06F17/5031

摘要： Static timing and/or noise analysis are performed on a netlist of an integrated circuit, to estimate behavior of the netlist and to identify at least one violation by said behavior of a corresponding requirement thereon, such as setup time, hold time or bump height in a quiescent net. Thereafter, effect of engineering change order (ECO) to correct the violation are automatically analyzed, based on the layout, the parasitics, the timing and/or noise behavior, and the violation, followed by generation of a constraint on the behavior (called “ECO” constraint), such as a timing constraint and/or a noise constraint. Next, the ECO constraint is automatically used, e.g. in a place and route tool, to select an ECO repair technique, from several ECO repair techniques that can overcome the violation. The selected ECO repair technique is automatically applied to the layout, to generate a modified layout which does not have the violation.

公开(公告)号：US20110113396A1

公开(公告)日：2011-05-12

申请号：US13007665

申请日：2011-01-17

申请人： Nahmsuk Oh ,  Peivand Fallah-Tehrani ,  Alireza Kasnavi ,  Subramanyam Sripada

发明人： Nahmsuk Oh ,  Peivand Fallah-Tehrani ,  Alireza Kasnavi ,  Subramanyam Sripada

IPC分类号： G06F17/50

CPC分类号： G06F17/5068 ,  G06F17/5036

摘要： A computer-implemented method of determining an attribute of a circuit includes using a computationally expensive technique to simulate the attribute (such as timing delay or slew) of a portion of the circuit, at predetermined values of various parameters (e.g. nominal values of channel length or metal width), to obtain at least a first value of the attribute. The method also uses a computationally inexpensive technique to estimate the same attribute, thereby to obtain at least a second value which is less accurate than the first value. Then the computationally inexpensive technique is repeatedly used on other values of the parameter(s), to obtain a number of additional second values of the attribute. Applying to the additional second values, a function obtained by calibrating the at least one second value to the at least one first value, can yield calibrated estimates very quickly, which represent the attribute's variation relatively accurately.

摘要翻译： 计算机实现的确定电路属性的方法包括使用计算上昂贵的技术来模拟电路的一部分的属性（例如定时延迟或转换），在各种参数的预定值（例如，信道长度的标称值 或金属宽度），以获得属性的至少第一值。 该方法还使用计算上便宜的技术来估计相同的属性，从而获得至少比第一值更不准确的第二值。 然后，在参数的其他值上重复使用计算上便宜的技术，以获得属性的附加第二值的数量。 应用附加的第二值，通过将至少一个第二值​​校准为至少一个第一值而获得的函数可以非常快地产生校正的估计，其相对准确地表示属性的变化。

公开(公告)号：US07900165B2

公开(公告)日：2011-03-01

申请号：US11731565

申请日：2007-03-30

申请人： Nahmsuk Oh ,  Peivand Fallah-Tehrani ,  Alireza Kasnavi ,  Subramanyam Sripada

发明人： Nahmsuk Oh ,  Peivand Fallah-Tehrani ,  Alireza Kasnavi ,  Subramanyam Sripada

IPC分类号： G06F17/50 ,  G06F9/45 ,  G06F17/10

CPC分类号： G06F17/5068 ,  G06F17/5036

摘要： A computer-implemented method of determining an attribute of a circuit includes using a computationally expensive technique to simulate the attribute (such as timing delay or slew) of a portion of the circuit, at predetermined values of various parameters (e.g. nominal values of channel length or metal width), to obtain at least a first value of the attribute. The method also uses a computationally inexpensive technique to estimate the same attribute, thereby to obtain at least a second value which is less accurate than the first value. Then the computationally inexpensive technique is repeatedly used on other values of the parameter(s), to obtain a number of additional second values of the attribute. Applying to the additional second values, a function obtained by calibrating the at least one second value to the at least one first value, can yield calibrated estimates very quickly, which represent the attribute's variation relatively accurately.

摘要翻译： 计算机实现的确定电路属性的方法包括使用计算上昂贵的技术来模拟电路的一部分的属性（例如定时延迟或转换），在各种参数的预定值（例如，信道长度的标称值 或金属宽度），以获得属性的至少第一值。 该方法还使用计算上便宜的技术来估计相同的属性，从而获得至少比第一值更不准确的第二值。 然后，在参数的其他值上重复使用计算上便宜的技术，以获得属性的附加第二值的数量。 应用附加的第二值，通过将至少一个第二值​​校准为至少一个第一值而获得的函数可以非常快地产生校正的估计，其相对准确地表示属性的变化。

公开(公告)号：US20090055787A1

公开(公告)日：2009-02-26

申请号：US12263447

申请日：2008-10-31

申请人： Nahmsuk Oh ,  Peivand Fallah-Tehrani ,  Alireza Kasnavi

发明人： Nahmsuk Oh ,  Peivand Fallah-Tehrani ,  Alireza Kasnavi

IPC分类号： G06F17/50

CPC分类号： G06F17/5022 ,  G06F17/5031

摘要： Static timing and/or noise analysis are performed on a netlist of an integrated circuit, to estimate behavior of the netlist and to identify at least one violation by said behavior of a corresponding requirement thereon, such as setup time, hold time or bump height in a quiescent net. Thereafter, effect of engineering change order (ECO) to correct the violation are automatically analyzed, based on the layout, the parasitics, the timing and/or noise behavior, and the violation, followed by generation of a constraint on the behavior (called “ECO” constraint), such as a timing constraint and/or a noise constraint. Next, the ECO constraint is automatically used, e.g. in a place and route tool, to select an ECO repair technique, from several ECO repair techniques that can overcome the violation. The selected ECO repair technique is automatically applied to the layout, to generate a modified layout which does not have the violation.

摘要翻译： 静态时序和/或噪声分析在集成电路的网表上执行，以估计网表的行为，并通过其上的相应要求的所述行为识别至少一个违规，诸如建立时间，保持时间或突发高度 一个静止网。 此后，根据布局，寄生效应，时间安排和/或噪音行为以及违规行为自动分析工程变更单（ECO）对违规行为的影响，随后对行为产生约束（称为“ ECO“约束），诸如时序约束和/或噪声约束。 接下来，自动使用ECO约束。 在地方和路线工具中，选择一种ECO修复技术，从几种可以克服违规的ECO修复技术。 选择的ECO修复技术自动应用于布局，以生成不具有违规的修改的布局。

公开(公告)号：US20080243414A1

公开(公告)日：2008-10-02

申请号：US11731565

申请日：2007-03-30

申请人： Nahmsuk Oh ,  Peivand Fallah-Tehrani ,  Alireza Kasnavi ,  Subramanyam Sripada

发明人： Nahmsuk Oh ,  Peivand Fallah-Tehrani ,  Alireza Kasnavi ,  Subramanyam Sripada

IPC分类号： G01D21/00

CPC分类号： G06F17/5068 ,  G06F17/5036

摘要： A computer-implemented method of determining an attribute of a circuit includes using a computationally expensive technique to simulate the attribute (such as timing delay or slew) of a portion of the circuit, at predetermined values of various parameters (e.g. nominal values of channel length or metal width), to obtain at least a first value of the attribute. The method also uses a computationally inexpensive technique to estimate the same attribute, thereby to obtain at least a second value which is less accurate than the first value. Then the computationally inexpensive technique is repeatedly used on other values of the parameter(s), to obtain a number of additional second values of the attribute. Applying to the additional second values, a function obtained by calibrating the at least one second value to the at least one first value, can yield calibrated estimates very quickly, which represent the attribute's variation relatively accurately.

摘要翻译： 计算机实现的确定电路属性的方法包括使用计算上昂贵的技术来模拟电路的一部分的属性（例如定时延迟或转换），在各种参数的预定值（例如，信道长度的标称值 或金属宽度），以获得属性的至少第一值。 该方法还使用计算上便宜的技术来估计相同的属性，从而获得至少比第一值更不准确的第二值。 然后，在参数的其他值上重复使用计算上便宜的技术，以获得属性的附加第二值的数量。 应用附加的第二值，通过将至少一个第二值​​校准为至少一个第一值而获得的函数可以非常快地产生校正的估计，其相对准确地表示属性的变化。