公开(公告)号：US07272807B2

公开(公告)日：2007-09-18

申请号：US11071121

申请日：2005-03-02

申请人： Li Ding ,  Peivand Fallah Tehrani ,  Alireza Kasnavi

发明人： Li Ding ,  Peivand Fallah Tehrani ,  Alireza Kasnavi

IPC分类号： G06F17/50

CPC分类号： G06F17/5036 ,  G06F17/5031

摘要： An equivalent waveform for a distorted waveform used in timing and signal integrity analysis in the design of an integrated circuit is automatically generated. The equivalent waveform is produced by calculating the transition quantity of a first non-distorted waveform. The transition quantity is the amount of transition of the first non-distorted waveform that is required for the cell to produce an output waveform with a predetermined end voltage. The end point of the transition period for the distorted waveform is then determined based on when the distorted waveform has accumulated the same transition quantity. The equivalent waveform can then be formed by computing a second non-distorted waveform such that the end point of the transition period for the second non-distorted waveform coincides with the end point of the transition period for the distorted waveform.

摘要翻译： 自动生成在集成电路设计中用于定时和信号完整性分析的失真波形的等效波形。 通过计算第一非失真波形的转移量来产生等效波形。 转换量是单元格产生具有预定端电压的输出波形所需的第一非失真波形的转变量。 然后，基于失真波形累积相同过渡量的时间来确定失真波形的转换周期的终点。 然后可以通过计算第二非失真波形来形成等效波形，使得第二非失真波形的转换周期的终点与失真波形的过渡周期的终点重合。

公开(公告)号：US20070010981A1

公开(公告)日：2007-01-11

申请号：US11166659

申请日：2005-06-23

申请人： Li Ding ,  Peivand Fallah-Tehrani ,  Alireza Kasnavi

发明人： Li Ding ,  Peivand Fallah-Tehrani ,  Alireza Kasnavi

IPC分类号： G06F17/50

CPC分类号： G06F17/5031

摘要： A model for a circuit cell used in timing and signal integrity analysis in an integrated circuit design is automatically generated. A behavioral model, such as a gate current model is used in which the current in the circuit cell is determined as a function of the input voltage and the output voltage of the circuit cell as well as the history of at least one of the current, voltage, and charge values of the circuit cell. For example, the current in the circuit cell may be a function of the history of the current, which may be calculated incrementally using recursive convolution at each time step when using the model.

摘要翻译： 自动生成用于集成电路设计中的时序和信号完整性分析的电路单元的模型。 使用诸如栅极电流模型的行为模型，其中电路单元中的电流被确定为电路单元的输入电压和输出电压的函数以及电流单元中的至少一个的历史， 电压和电荷值。 例如，电路单元中的电流可以是电流的历史的函数，其可以在使用该模型时在每个时间步长处使用递归卷积来逐渐计算。

公开(公告)号：US08478573B2

公开(公告)日：2013-07-02

申请号：US11166659

申请日：2005-06-23

申请人： Li Ding ,  Peivand Fallah-Tehrani ,  Alireza Kasnavi

发明人： Li Ding ,  Peivand Fallah-Tehrani ,  Alireza Kasnavi

IPC分类号： G06F17/50

CPC分类号： G06F17/5031

摘要： A model for a circuit cell used in timing and signal integrity analysis in an integrated circuit design is automatically generated. A behavioral model, such as a gate current model is used in which the current in the circuit cell is determined as a function of the input voltage and the output voltage of the circuit cell as well as the history of at least one of the current, voltage, and charge values of the circuit cell. For example, the current in the circuit cell may be a function of the history of the current, which may be calculated incrementally using recursive convolution at each time step when using the model.

摘要翻译： 自动生成用于集成电路设计中的时序和信号完整性分析的电路单元的模型。 使用诸如栅极电流模型的行为模型，其中电路单元中的电流被确定为电路单元的输入电压和输出电压的函数以及电流单元中的至少一个的历史， 电压和电荷值。 例如，电路单元中的电流可以是电流的历史的函数，其可以在使用该模型时在每个时间步长处使用递归卷积来逐渐计算。

公开(公告)号：US20060200784A1

公开(公告)日：2006-09-07

申请号：US11071121

申请日：2005-03-02

申请人： Li Ding ,  Peivand Fallah-Tehrani ,  Alireza Kasnavi

发明人： Li Ding ,  Peivand Fallah-Tehrani ,  Alireza Kasnavi

IPC分类号： G06F17/50

CPC分类号： G06F17/5036 ,  G06F17/5031

摘要： An equivalent waveform for a distorted waveform used in timing and signal integrity analysis in the design of an integrated circuit is automatically generated. The equivalent waveform is produced by calculating the transition quantity of a first non-distorted waveform. The transition quantity is the amount of transition of the first non-distorted waveform that is required for the cell to produce an output waveform with a predetermined end voltage. The end point of the transition period for the distorted waveform is then determined based on when the distorted waveform has accumulated the same transition quantity. The equivalent waveform can then be formed by computing a second non-distorted waveform such that the end point of the transition period for the second non-distorted waveform coincides with the end point of the transition period for the distorted waveform.

摘要翻译： 自动生成在集成电路设计中用于定时和信号完整性分析的失真波形的等效波形。 通过计算第一非失真波形的转移量来产生等效波形。 转换量是单元格产生具有预定端电压的输出波形所需的第一非失真波形的转变量。 然后，基于失真波形累积相同过渡量的时间来确定失真波形的转换周期的终点。 然后可以通过计算第二非失真波形来形成等效波形，使得第二非失真波形的转换周期的终点与失真波形的过渡周期的终点重合。

公开(公告)号：US07861198B2

公开(公告)日：2010-12-28

申请号：US11863252

申请日：2007-09-28

申请人： Li Ding ,  Peivand Tehrani ,  Jindrich Zejda ,  Alireza Kasnavi

发明人： Li Ding ,  Peivand Tehrani ,  Jindrich Zejda ,  Alireza Kasnavi

IPC分类号： G06F17/50

CPC分类号： G06F17/5031

摘要： A method to perform timing analysis for a complex logic cell with distorted input waveform and coupled load networks is presented. Timing arc based models are used in conjunction with CCB based current models of portions of the logic cell to compute the output signal of the logic cell. For example, an intermediary signal is generated using a first timing arc based model and an equivalent coupled network output signal is generated using a channel connected block (CCB) based current model.

摘要翻译： 提出了一种对具有失真输入波形和耦合负载网络的复杂逻辑单元执行定时分析的方法。 基于时间弧的模型与基于CCB的当前模型的逻辑单元的部分结合使用以计算逻辑单元的输出信号。 例如，使用基于第一定时弧的模型生成中间信号，并且使用基于信道连接块（CCB）的当前模型生成等效的耦合网络输出信号。

公开(公告)号：US08341574B2

公开(公告)日：2012-12-25

申请号：US12399704

申请日：2009-03-06

申请人： Ravikishore Gandikota ,  Li Ding ,  Peivand Tehrani ,  Nahmsuk Oh ,  Alireza Kasnavi

发明人： Ravikishore Gandikota ,  Li Ding ,  Peivand Tehrani ,  Nahmsuk Oh ,  Alireza Kasnavi

IPC分类号： G06F17/50

CPC分类号： G06F17/5031 ,  G06F2217/84

摘要： Embodiments of a computer system, a method, an integrated circuit and a computer-program product (i.e., software) for use with the computer system are described. These devices and techniques may be used to calculate the total time delay in a signal path due to crosstalk from a group of crosstalk aggressors that are associated with a group of signal paths. In order to properly account for statistical behaviors in the switching times and directions of the switching patterns in the group of signal paths, the time-delay contribution from each of these crosstalk aggressors may be modeled as a corresponding statistical random variable. Because the number of crosstalk aggressors are usually much larger than the number of stages in the signal path, the calculated total path delay may be less pessimistic. Furthermore, in order to detect potential timing violations, the time-delay contributions from additional dominant crosstalk aggressors can be modeled using non-statistical worst-case deterministic values.

摘要翻译： 描述了与计算机系统一起使用的计算机系统，方法，集成电路和计算机程序产品（即，软件）的实施例。 这些装置和技术可用于计算由于与一组信号路径相关联的一组串扰侵扰者的串扰引起的信号路径中的总时间延迟。 为了适当地考虑信号路径组中的切换模式的切换时间和方向的统计行为，来自每个这些串扰侵略者的时间延迟贡献可以被建模为相应的统计随机变量。 因为串扰攻击者的数量通常远大于信号路径中的级数，所以计算的总路径延迟可能不那么悲观。 此外，为了检测潜在的定时违规，可以使用非统计最坏情况确定性值来对附加的主要串扰侵扰者的时间延迟贡献进行建模。

公开(公告)号：US20100229136A1

公开(公告)日：2010-09-09

申请号：US12399704

申请日：2009-03-06

申请人： Ravikishore Gandikota ,  Li Ding ,  Peivand Tehrani ,  Nahmsuk Oh ,  Alireza Kasnavi

发明人： Ravikishore Gandikota ,  Li Ding ,  Peivand Tehrani ,  Nahmsuk Oh ,  Alireza Kasnavi

IPC分类号： G06F17/50

CPC分类号： G06F17/5031 ,  G06F2217/84

摘要： Embodiments of a computer system, a method, an integrated circuit and a computer-program product (i.e., software) for use with the computer system are described. These devices and techniques may be used to calculate the total time delay in a signal path due to crosstalk from a group of crosstalk aggressors that are associated with a group of signal paths. In order to properly account for statistical behaviors in the switching times and directions of the switching patterns in the group of signal paths, the time-delay contribution from each of these crosstalk aggressors may be modeled as a corresponding statistical random variable. Because the number of crosstalk aggressors are usually much larger than the number of stages in the signal path, the calculated total path delay may be less pessimistic. Furthermore, in order to detect potential timing violations, the time-delay contributions from additional dominant crosstalk aggressors can be modeled using non-statistical worst-case deterministic values.

摘要翻译： 描述了与计算机系统一起使用的计算机系统，方法，集成电路和计算机程序产品（即，软件）的实施例。 这些装置和技术可用于计算由于与一组信号路径相关联的一组串扰侵扰者的串扰引起的信号路径中的总时间延迟。 为了适当地考虑信号路径组中的切换模式的切换时间和方向的统计行为，来自每个这些串扰侵略者的时间延迟贡献可以被建模为相应的统计随机变量。 因为串扰攻击者的数量通常远大于信号路径中的级数，所以计算的总路径延迟可能不那么悲观。 此外，为了检测潜在的定时违规，可以使用非统计最坏情况确定性值来对附加的主要串扰侵扰者的时间延迟贡献进行建模。

公开(公告)号：US20100198539A1

公开(公告)日：2010-08-05

申请号：US12363373

申请日：2009-01-30

申请人： Hong Li ,  Li Ding ,  Alireza Kasnavi

发明人： Hong Li ,  Li Ding ,  Alireza Kasnavi

IPC分类号： G01R27/26 ,  G01R27/00

CPC分类号： G06F17/5036

摘要： Embodiments of a computer system, a method, an integrated circuit and a computer-program product (i.e., software) for use with the computer system are described. These devices and techniques may be used to analyze an electrical characteristic of a logic gate electrically coupled to an output network in a stage. In particular, during the analysis, the effective capacitance of an output network coupled to a logic gate is approximated as a function of a total resistance of the output network, a total capacitance of the output network, and a geometric parameter of the output network. For example, the effective capacitance may be approximated as a function of a ratio of the product of the total resistance and the total capacitance to the fanout count of the output network. Using the effective capacitance and other parameters, such as a slew rate of an electrical signal applied to an input of the logic gate, an electrical characteristic of the logic gate, such as an input capacitance, is determined.

摘要翻译： 描述了与计算机系统一起使用的计算机系统，方法，集成电路和计算机程序产品（即，软件）的实施例。 这些装置和技术可以用于分析在一个级中电耦合到输出网络的逻辑门的电特性。 特别地，在分析期间，耦合到逻辑门的输出网络的有效电容被近似为输出网络的总电阻，输出网络的总电容和输出网络的几何参数的函数。 例如，有效电容可以近似为总电阻和总电容的乘积与输出网络的扇出计数之比的函数。 使用诸如施加到逻辑门的输入端的电信号的转换速率等有效电容和其他参数，确定诸如输入电容的逻辑门的电特性。

公开(公告)号：US08145442B2

公开(公告)日：2012-03-27

申请号：US12363373

申请日：2009-01-30

申请人： Hong Li ,  Li Ding ,  Alireza Kasnavi

发明人： Hong Li ,  Li Ding ,  Alireza Kasnavi

IPC分类号： G01R27/26 ,  G06F17/40

CPC分类号： G06F17/5036

摘要： Embodiments of a computer system, a method, an integrated circuit and a computer-program product (i.e., software) for use with the computer system are described. These devices and techniques may be used to analyze an electrical characteristic of a logic gate electrically coupled to an output network in a stage. In particular, during the analysis, the effective capacitance of an output network coupled to a logic gate is approximated as a function of a total resistance of the output network, a total capacitance of the output network, and a geometric parameter of the output network. Using the effective capacitance and other parameters, such as a slew rate of an electrical signal applied to an input of the logic gate, an electrical characteristic of the logic gate, such as an input capacitance, is determined.

摘要翻译： 描述了与计算机系统一起使用的计算机系统，方法，集成电路和计算机程序产品（即，软件）的实施例。 这些装置和技术可以用于分析在一个级中电耦合到输出网络的逻辑门的电特性。 特别地，在分析期间，耦合到逻辑门的输出网络的有效电容被近似为输出网络的总电阻，输出网络的总电容和输出网络的几何参数的函数。 使用诸如施加到逻辑门的输入端的电信号的转换速率等有效电容和其他参数，确定诸如输入电容的逻辑门的电特性。

公开(公告)号：US20090089729A1

公开(公告)日：2009-04-02

申请号：US11863252

申请日：2007-09-28

申请人： Li Ding ,  Peivand Tehrani ,  Jindrich Zejda ,  Alireza Kasnavi

发明人： Li Ding ,  Peivand Tehrani ,  Jindrich Zejda ,  Alireza Kasnavi

IPC分类号： G06F17/50

CPC分类号： G06F17/5031

摘要： A method to perform timing analysis for a complex logic cell with distorted input waveform and coupled load networks is presented. Timing arc based models are used in conjunction with CCB based current models of portions of the logic cell to compute the output signal of the logic cell. For example, an intermediary signal is generated using a first timing arc based model and an equivalent coupled network output signal is generated using a channel connected block (CCB) based current model.

摘要翻译： 提出了一种对具有失真输入波形和耦合负载网络的复杂逻辑单元执行定时分析的方法。 基于时间弧的模型与基于CCB的当前模型的逻辑单元的部分结合使用以计算逻辑单元的输出信号。 例如，使用基于第一定时弧的模型生成中间信号，并且使用基于信道连接块（CCB）的当前模型生成等效的耦合网络输出信号。