公开(公告)号：US10956346B1

公开(公告)日：2021-03-23

申请号：US15857756

申请日：2017-12-29

申请人： Lightbits Labs Ltd.

发明人： Shmuel Ben-Yehuda ,  Ofir Efrati ,  Sagi Grimberg ,  Eran Kirzner ,  Ziv Tishel ,  Fabian Trumper

IPC分类号： G06F13/28 ,  G06F13/16 ,  G06F3/06

摘要： A storage system that includes an in-line hardware accelerator, a solid-state drive (SSD) unit, a central processing unit (CPU), a volatile memory module, and an accelerator memory module that is coupled to the in-line hardware accelerator or belongs to the in-line hardware accelerator; wherein the in-line hardware accelerator is directly coupled to the SSD unit, the volatile memory and the non-volatile memory; wherein the CPU is directly coupled to the volatile memory and to the non-volatile memory; wherein the in-line hardware accelerator is configured to manage access to the SSD unit; wherein the in-line accelerator is configured to retrieve data stored in the volatile memory module and the non-volatile memory module without involving the CPU.

公开(公告)号：US10963393B1

公开(公告)日：2021-03-30

申请号：US15857758

申请日：2017-12-29

申请人： LIGHTBITS LABS LTD.

发明人： Shmuel Ben-Yehuda ,  Ofir Efrati ,  Abel Alkon Gordon ,  Eran Kirzner ,  Fabian Trumper

IPC分类号： G06F12/10 ,  G06F13/16 ,  G06F13/40 ,  G06F13/28

摘要： A method for accessing a storage system, the method may include receiving a block call, from a processor that executes an application and by a storage engine of a computer that is coupled to a storage system; generating, by the storage engine and based on the block call, a key value call; and sending the key value call to a key value frontend of the storage system.

公开(公告)号：US11256431B1

公开(公告)日：2022-02-22

申请号：US15857761

申请日：2017-12-29

申请人： Lightbits Labs Ltd.

发明人： Shmuel Ben-Yehuda ,  Ofir Efrati ,  Sagi Grimberg ,  Eran Kirzner ,  Ziv Tishel ,  Fabian Trumper

IPC分类号： G06F3/06

摘要： A field programmable gate array (FPGA), that includes a trusted FPGA logic, an untrusted FPGA logic and a monitor; wherein the monitor is configured to monitor the untrusted FPGA logic and prevent the untrusted FPGA logic from violating predefined constrains imposed on an operation of the untrusted FPGA logic; wherein the predefined constraints are stored in a memory region of the FPGA that is not accessible to the untrusted FPGA logic.