公开(公告)号：US20150362936A1

公开(公告)日：2015-12-17

申请号：US14706555

申请日：2015-05-07

Applicant: Linear Technology Corporation

Inventor： Amitkumar P. Patel ,  Carl Nelson

IPC: G05F1/575

CPC classification number: G05F1/575 ,  G05F1/563 ,  G05F1/59 ,  H02M2001/007

Abstract: In an LDO regulator, two feedback loops are created. The first feedback loop includes a high power PNP bipolar power transistor connected in series between the input voltage Vin terminal and the output voltage Vout terminal. The first feedback loop includes a first error amplifier that controls a drive transistor to drive the base of the power transistor such that Vout matches a set voltage Vset. This first feedback loop circuitry uses an operating voltage (the upper rail voltage) that is regulated by a second feedback loop and is approximately 300 mV greater than Vout. As a result, the control circuitry will be powered by a low ripple supply to improve output PSRR. Further, the power transistor is connected such that any noise in the input voltage is a common mode voltage across the base-emitter of the transistor.

Abstract translation: 在LDO调节器中，创建了两个反馈回路。 第一反馈回路包括串联连接在输入电压Vin端和输出电压Vout端之间的高功率PNP双极功率晶体管。 第一反馈回路包括第一误差放大器，其控制驱动晶体管驱动功率晶体管的基极，使得Vout匹配设定电压Vset。 该第一反馈回路电路使用由第二反馈回路调节的工作电压（上轨电压），并且比Vout大大约300mV。 因此，控制电路将由低纹波电源供电，以改善输出PSRR。 此外，功率晶体管被连接成使得输入电压中的任何噪声都是晶体管的基极 - 发射极两端的共模电压。

公开(公告)号：US20150362935A1

公开(公告)日：2015-12-17

申请号：US14706527

申请日：2015-05-07

Applicant: Linear Technology Corporation

Inventor： Amitkumar P. Patel ,  Anthony K. Bonte

IPC: G05F1/575

CPC classification number: G05F1/575 ,  G05F1/563 ,  G05F1/59 ,  H02M2001/007

Abstract: A driver circuit for a PNP power transistor in an LDO regulator uses a Class AB (push-pull) buffer to supply the necessary base current to an NPN driver transistor, where the NPN driver transistor has its collector connected to the base of the PNP power transistor. A front end circuit of the driver, coupled to drive the Class AB buffer, uses a current diverting transistor, where a first portion of the current is used to control the pull-up transistor in the Class AB buffer, and the remainder of the current is used to control the pull-down transistor in the Class AB buffer, so the driver is very efficient. The portion of the driver circuit between the input of the driver circuit and the base of the NPN driver transistor is an inverting circuit. The driver can properly operate with an input voltage within two diode drops of ground.

Abstract translation: 用于LDO稳压器中的PNP功率晶体管的驱动电路使用AB类（推挽）缓冲器向NPN驱动晶体管提供所需的基极电流，其中NPN驱动晶体管的集电极连接到PNP功率的基极 晶体管。 驱动AB驱动器的前端电路使用一个电流转向晶体管，其中第一部分电流用于控制AB类缓冲器中的上拉晶体管，其余的电流 用于控制AB类缓冲器中的下拉晶体管，因此驱动器非常有效。 驱动电路的输入端与NPN驱动晶体管的基极之间的驱动电路部分是反相电路。 驱动器可以在两个二极管接地端内的输入电压下正常工作。

公开(公告)号：US09632519B2

公开(公告)日：2017-04-25

申请号：US14706527

申请日：2015-05-07

Applicant: Linear Technology Corporation

Inventor： Amitkumar P. Patel ,  Anthony K. Bonte

IPC: G05F1/56 ,  G05F1/575 ,  G05F1/563 ,  G05F1/59 ,  H02M1/00

CPC classification number: G05F1/575 ,  G05F1/563 ,  G05F1/59 ,  H02M2001/007

Abstract: A driver circuit for a PNP power transistor in an LDO regulator uses a Class AB (push-pull) buffer to supply the necessary base current to an NPN driver transistor, where the NPN driver transistor has its collector connected to the base of the PNP power transistor. A front end circuit of the driver, coupled to drive the Class AB buffer, uses a current diverting transistor, where a first portion of the current is used to control the pull-up transistor in the Class AB buffer, and the remainder of the current is used to control the pull-down transistor in the Class AB buffer, so the driver is very efficient. The portion of the driver circuit between the input of the driver circuit and the base of the NPN driver transistor is an inverting circuit. The driver can properly operate with an input voltage within two diode drops of ground.

公开(公告)号：US09454168B2

公开(公告)日：2016-09-27

申请号：US14706555

申请日：2015-05-07

Applicant: Linear Technology Corporation

Inventor： Amitkumar P. Patel ,  Carl Nelson

IPC: G05F1/575 ,  G05F1/563 ,  G05F1/59 ,  H02M1/00

CPC classification number: G05F1/575 ,  G05F1/563 ,  G05F1/59 ,  H02M2001/007

Abstract: In an LDO regulator, two feedback loops are created. The first feedback loop includes a high power PNP bipolar power transistor connected in series between the input voltage Vin terminal and the output voltage Vout terminal. The first feedback loop includes a first error amplifier that controls a drive transistor to drive the base of the power transistor such that Vout matches a set voltage Vset. This first feedback loop circuitry uses an operating voltage (the upper rail voltage) that is regulated by a second feedback loop and is approximately 300 mV greater than Vout. As a result, the control circuitry will be powered by a low ripple supply to improve output PSRR. Further, the power transistor is connected such that any noise in the input voltage is a common mode voltage across the base-emitter of the transistor.

Abstract translation: 在LDO调节器中，创建了两个反馈回路。 第一反馈回路包括串联连接在输入电压Vin端和输出电压Vout端之间的高功率PNP双极功率晶体管。 第一反馈回路包括第一误差放大器，其控制驱动晶体管驱动功率晶体管的基极，使得Vout匹配设定电压Vset。 该第一反馈回路电路使用由第二反馈回路调节的工作电压（上轨电压），并且比Vout大大约300mV。 因此，控制电路将由低纹波电源供电，以改善输出PSRR。 此外，功率晶体管被连接成使得输入电压中的任何噪声都是晶体管的基极 - 发射极两端的共模电压。