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    Balancing techniques and circuits for charge pumps
    3.
    发明授权
    Balancing techniques and circuits for charge pumps 有权

    公开(公告)号：US10468978B2

    公开(公告)日：2019-11-05

    申请号：US15465487

    申请日：2017-03-21

    Applicant: Linear Technology Corporation

    Inventor： Xu Zhang ,  Jian Li ,  San Hwa Chee

    IPC: H02M3/07 ,  H02M1/36 ,  H02M1/08

    Abstract: Methods and systems of pre-balancing a switched capacitor converter are provided. A first comparator includes a positive input configured to receive a voltage across an output capacitor and a negative input configured to receive a first hysteresis voltage. A second comparator includes a positive input configured to receive a voltage across an input capacitor of the switched capacitor converter and a negative input configured to receive a second hysteresis voltage. A first current source is coupled between the output capacitor and GND and is configured to discharge the output capacitor upon determining that the voltage across the output capacitor is above a tolerance provided by the first hysteresis voltage. A second current source is coupled between the input capacitor and GND and is configured to discharge the input capacitor upon determining that the voltage across the input capacitor is above a tolerance provided by the second hysteresis voltage.

    Low power timing, configuring, and scheduling
    5.
    发明授权
    Low power timing, configuring, and scheduling 有权

    公开(公告)号：US10152111B2

    公开(公告)日：2018-12-11

    申请号：US15728453

    申请日：2017-10-09

    Applicant: Linear Technology Corporation

    Inventor： Brett Warneke ,  Maxim Moiseev

    IPC: G06F1/32 ,  G06F1/12 ,  G06F9/44 ,  H03L5/02 ,  H03L7/18 ,  H04W52/02 ,  H04B1/00 ,  G06F9/445 ,  G06F1/14

    Abstract: A network device includes a network interface circuit, a microprocessor, a timing circuit, and a microsequencer. The timing circuit is configured to, based on a primary timing signal, generate a time signature and switch the network device from an inactive state to an active state when the time signature satisfies a predetermined threshold length of time for packet transmission. The microsequencer circuit is configured to, in response to the network device being switched to the active state, activate and configure the network interface circuit for the packet transmission, independent of the microprocessor and delays encountered by the microprocessor. The device also reduces energy consumption by using a lower frequency secondary oscillator to maintain timing information when a higher frequency primary oscillator is inactivated.

    DISJOINT SECURITY IN WIRELESS NETWORKS WITH MULTIPLE MANAGERS OR ACCESS POINTS
    6.
    发明申请
    DISJOINT SECURITY IN WIRELESS NETWORKS WITH MULTIPLE MANAGERS OR ACCESS POINTS 审中-公开

    公开(公告)号：US20180317089A1

    公开(公告)日：2018-11-01

    申请号：US15963055

    申请日：2018-04-25

    Applicant: Linear Technology Corporation

    Inventor： Alain Pierre LEVESQUE ,  Aleksandr LUSHIN ,  David Ramsay Hanson BACHER ,  Lance Robert DOHERTY

    IPC: H04W12/06 ,  H04W8/30 ,  H04L29/08 ,  H04W12/04 ,  H04L9/08

    Abstract: In a wireless mesh network having multiple network managers, the network managers maintain network security through the use of encryption keys and packet counters. To ensure that each network manager can authenticate communications with any node of the network, the authentication data is replicated in a disjoint manner in all network managers. Advantageously, network reliability is assured by providing redundant managers that can seamlessly maintain network operation even if multiple network managers fail; newly joining managers can obtain full authentication data for the network upon joining; and network throughput is increased by ensuring that any of the multiple managers can authenticate the communications of any network node. The disjoint replication of the authentication data across all network managers is performed with low data-rate manager-to-manager packets propagated through the network. The disjoint security methods and systems can advantageously be used in wireless battery monitoring systems, for example.

    METHODS AND SYSTEMS OF REDUCING CHARGE PUMP SUBSTRATE NOISE
    8.
    发明申请
    METHODS AND SYSTEMS OF REDUCING CHARGE PUMP SUBSTRATE NOISE 审中-公开

    公开(公告)号：US20180248476A1

    公开(公告)日：2018-08-30

    申请号：US15445926

    申请日：2017-02-28

    Applicant: Linear Technology Corporation

    Inventor： Barry Harvey

    IPC: H02M3/07

    Abstract: Methods and systems of reducing a substrate noise in a charge pump having a flying capacitor are provided. An input node of the flying capacitor is pre-charged at a first slew rate. The input node of the flying capacitor is charged at a second slew rate that is faster than the first slew rate. The input node of the flying capacitor is pre-discharged at a third slew rate. The input node of the flying capacitor is discharged at a fourth slew rate that is faster than the first slew rate.

    DETECTION AND CLASSIFICATION SCHEME FOR POWER OVER ETHERNET SYSTEM
    9.
    发明申请
    DETECTION AND CLASSIFICATION SCHEME FOR POWER OVER ETHERNET SYSTEM 审中-公开

    公开(公告)号：US20180129171A1

    公开(公告)日：2018-05-10

    申请号：US15863571

    申请日：2018-01-05

    Applicant: Linear Technology Corporation

    Inventor： David Dwelley ,  Jeffrey Heath ,  Kirk Su ,  Ryan Huff

    IPC: G05B11/01 ,  H04L12/10 ,  H02J3/00

    CPC classification number: G05B11/01 ,  H02J3/00 ,  H04L12/10 ,  Y10T307/858

    Abstract: In a method performed by a PoE system, a PSE provides data and operating voltage over Ethernet wires to a PD. Before the full PoE voltage is supplied, the PSE generates a low current signal received by the PD. A circuit in the PD, connected across its input terminals, has a characteristic analog response to the PSE signal corresponding to the PD's PoE requirements, such as whether the PD is a Type 1 or Type 2 PD. The circuit may be a certain value capacitor, zener diode, resistor, or other circuit. The PSE may generate a fixed current, fixed voltage, or time varying signal. Upon the PSE sensing the magnitude of the analog signal response at a particular time, the PSE associates the response with the PoE requirements of the PD. The PSE then applies the full PoE voltage in accordance with the PD's PoE requirements.

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